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參數(shù)資料
| 型號(hào)： | S1T0567X01-D0B0 |
| 元件分類： | 信令電路 |
| 英文描述： | TELECOM, TONE DECODER CIRCUIT, PDIP8 |
| 封裝： | 0.300 INCH, DIP-8 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 561K |
| 代理商： | S1T0567X01-D0B0 |
TONE DECODER
S1T
0567
5
LARGEST DETECTION BANDWIDTH
The largest detection bandwidth is the largest frequency range within which an input signal above the threshold
voltage will cause a logical zero state at the output. The maximum detection bandwidth corresponds to the lock
range of the PLL.
Detection Bandwidth (BW)
The detection bandwidth is the frequency range centered about fO, within which an input signal larger than the
threshold voltage (typically 20 mVrms) will cause a logic zero state at the output. The detection bandwidth
corresponds to the capture range of the PLL and is determined by the Iow-pass filter. The bandwidth of the filter,
as a percent of fO, can be determined by the approximation
where Vi, is the input signal in volts, rms, and C2 is the capacitance at pin 2 in F.
Detection Band Skew
The detection band skew is a measure of how accurately the largest detection band is centered about the center
frequency, fO. It is defined as (fmax + fmin - 2fO)/fO, where fmax and fmin, are the frequencies corresponding to the
edges of the detection band. If necessary, the detection band skew can be reduced to zero by an optional centering
adjustment.
PIN DESCRIPTION
Output Filter-C3 (Pin 1)
Capacitor C3 connected from pin 1 to ground forms a simple low-pass post detection filter to eliminate spurious
outputs due to out-of-band signals. The time constant of the filter can be expressed as T3 = R3C3, where R3 (4.7k)
is the internal impedance at pin 1.
The precise value of C3 is not practical for most applications. To eliminate the possibility of false triggering by
spurious signals, it is recommended that C3 be ≥ 2 C2. where C2 is the loop filter capacitance at pin 2.
If the value of C3 becomes too large, the turn-on or turn-off time of the output stage will be delayed until the voltage
change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable as a means of
suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at the output of the
quadrature detector may cause a false logic level change at the output. (Pin 8)
The average voltage (during lock) at pin 1 is a function of the inband input amplitude in accordance with the given
transfer characteristic.
Loop Filter - C2 (Pin 2)
Capacitor C2 connected from pin 2 to ground serves as a single pole, low-pass filter for the PLL portion of the
S1T0567.
The filter time constant is given by T2 = R2C2. where R2 (10k) is the impedance at pin 2.
The selection of C2 is determined by the detection bandwidth requirements. For additional information see the sec-
tion on “Definition of S1T0567 Parameters”.
The voltage at pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 to 1.05 fO,
with a slope of approximately 20 mV/% frequency deviation.
BW
1070
V
I
f
oC2
------------
=
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