參數(shù)資料
型號(hào)： S1R72005F00A300
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： QFP-64
文件頁(yè)數(shù)： 45/47頁(yè)
文件大?。?/td> 461K
代理商： S1R72005F00A300
1. Overview
S1R72005B00A300/F00A300
EPSON
1
Technical Manual (Rev.1.0)
1.
Overview
The LSI described in this manual is an On-The-Go device controller LSI compatible with USB 2.0-compliant Full
Speed (12 Mbps) mode. Both the Host and Peripheral functions as well as the On-The-Go function are integrated
onto a single chip, enabling the LSI to operate as a dual-role device.
In addition to providing universal connectivity between USB devices and a PC, the LSI offers a new feature that
permits unprecedented flexibility in the ways in which a USB device can be connected to another USB device. It
incorporates a CPU interface power supply (2.8 - 3.3 V) independent of the USB interface power supply (3.3 V),
allowing connection to various external CPUs.
2.
Features
Incorporates Host, Peripheral, and On-The-Go functions on a single chip.
Two I/O power supplies (USB 3.3 V and CPUIF 2.8 - 3.3 V).
Compliant with the On-The-Go (Supplement to the USB 2.0) 1.0 standard.
Supports USB 2.0 Full Speed (12 Mbps).
Provides one On-The-Go port.
Supports control, bulk, interrupt, and isochronous transfers.
Controller interface for reduced CPU loads and high throughput during USB transfers.
Supports Endpoint 0 and five general-purpose endpoints during peripheral operations.
Built-in 2.5-Kbyte FIFO for data transfers.
Uses a ring buffer-type FIFO.
Incorporates a 16-bit wide, general-purpose CPU interface.
Capable of operating as a 16-bit wide, general-purpose DMA slave (sharing buses with the CPU interface).
Accepts a 12 MHz resonator for clock input (built-in oscillator circuit).
Built-in frequency-multiplying PLL circuit.
Also accepts 12 MHz, 27 MHz, or 48 MHz external clock input from a crystal oscillator.
Sophisticated clock control for reduced power consumption.
Housed in an 81-pin CSP or 64-pin QFP package.
* The LSI is not designed to be radiation-resistant.
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