參數(shù)資料
型號: S1M8662A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CDMA/PCS/GPS Triple Mode IF/ baseband IC
中文描述: 碼分多址/件/全球定位系統(tǒng)三模式中頻/基帶IC
文件頁數(shù): 4/22頁
文件大?。?/td> 175K
代理商: S1M8662A
S1M8662A (Preliminary)
RX IF/BBA WITH GPS
4
PIN DESCRIPTION
Pin No
1
2
3
Symbol
VDDD
VDDA
RAGC_CONT
I/O
P
P
AI
Description
Power for the digital logic.
Power input terminal for the analog circuit.
AGC gain control input. The input voltage is allowed up to VDDA.
It remains at High impedance during SLEEP.
GPS IF input terminals, which have an input impedance of about
865W; generally, the GPS IF SAW filter is connected to them. When
these terminals are not used, they remain at High impedance.
CDMA IF input terminals, which have an input impedance of about
865
; generally, the CDMA IF SAW filter is connected to them. When
these terminals are not used, they remain at High impedance.
Power input terminal for the analog circuit.
TCXO Clock output. division ratio : 1
Power input terminal for the analog circuit.
Power input terminal for the analog circuit.
Control DC input for removing the DC offset generated in the
S1M8662A and system during CDMA and GPS Mode. The control DC
is generated in the modem in PDM form, passes through the R-C filter
and is converted to DC, which is sent to this input terminal.
Very sensitive terminal, which is connected to the oscillation L-C
resonance circuit.
Their impedance are about 2k
Power input terminal for the analog circuit.
Output for the PLL, able to output about -12dBm.
When this is not used, it remains at high impedance.
3-Line serial control. Strobe input port.
If this pin is opened, it remains at Low.
3-Line serial control. DATA input/output port.
If this pin is opened, it remains at Low.
3-Line serial control. CLOCK input/output port.
If this pin is opened, it remains at Low.
Reference frequency input terminal connected to the VCTCXO output.
When this pin stops, only DC bias is delivered to maintain the DC
charge value of the capacitor connected externally
CHIPx8 Clock input port. CDMA/GPS ADC sampling clock from the
MSM.
4
5
GRX_IF1
GRX_IF2
AI
6
7
CRX_IF1
CRX_IF2
AI
8
9
VDDA
TCXO_out
VDDA
VDDA
Q_OFS
I_OFS
P
DO
P
P
AI
10
11
12
13
14
15
RXVCO_T1
RXVCO_T2
AI
16
17
18
19
VDDA
P
RXVCO_OUT1
RXVCO_OUT2
SPI_STB
AO
DI
20
SPI_DATA
BI
21
SPI_CLK
DI
22
TCXO_in
AI/DI
23
CHIPx8
DI
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