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參數(shù)資料
| 型號： | S1M8657X01-F0T0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TX IF/BBA WITH AGC |
| 中文描述： | 德克薩斯州中頻/工商管理帶AGC |
| 文件頁數(shù)： | 24/34頁 |
| 文件大?。?/td> | 281K |
| 代理商： | S1M8657X01-F0T0 |
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S1M8657
TX IF/BBA WITH AGC
24
General Purpose ADC Basic-Mode Operation Using SPI
(SEN = high, TXMODE_CONT[0] = low)
SPI can be used when SEN= high. The GP-ADC operates in the basic mode. Under these circumstances, GP-
ADC is under the control of the SPI registers. The results of conversion can be output to not only the SPI register
GPADC_RSLT[7:0] but also to GPDATA and GPCLK. When the basic mode turns on and SPI starts, they are
automatically set. If the TXMODE_CONT[0] is "0" and all GP-ADC related controls and input/output function are
conducted through the SPI bus, the GP-ADC only outputs the SPI input/output. GPENA can also drive GP-ADC;
in this case, GPDATA and GPCLK are output and save at the same time in the SPI register, GPADC_RSLT[7:0].
In this mode, MODE_CONT[6:5] register holds the parallel input pins, SMSB/PAON and SLSB/CLK. If GPENA
changes from low to high or GPDAC_MODE[7] register from "0" to "1", the GP-ADC stars the conversion.
Essentially these indicate the start of conversion in basic mode. For a new conversion, these GPENA and
GDAC_MODE[7] must be left at low state and intialization starts at the rising edge of when they become high.
While conversion is going on, GP-ADC cannot receive any signals. GPADC_RSLT[7:0], which has the GP-ADC
conversion value, maintains its previous value until the end of the new conversion.
Table 7. GP-ADC Range Select in Basic Mode
GPADC_MODE[4]
0
0
0
0
1
1
1
1
TXNODE_CONT[6:5]
00
01
10
11
00
01
10
11
Vin Mid
1.0
2.0
1.5
1.5
0.75
1.5
1.5
1.5
Input Range
1.0
1.0
2.0
2.0
0.5
2.0
2.0
2.0
LSB(mV)
4
4
8
8
2
8
8
8
GPADC Input
GPIN1
GPIN1
GPIN2
GPIN3
GPIN1
GPIN1
GPIN2
GPIN3
Zin
∞
∞
∞
∞
∞
∞
∞
∞
GP-ADC can select from various input range as well as resolution value for each mid-voltage and LSB. It has a
built-in input switch, which allows for easy connection with the input sensor. All programmable options are set by
SPI registers TXMODE_CONT[6:5] and GOADC_MODE[4].
General Purpose ADC Conversion Time
GP-ADC conversion time is determined based on the TCXO and GP-ADC clock divide ratio in the SPI register
GPADC_MODE[7:6]. GP-ADC needs a total of 6 GPCLK cycles from its restart to start of data sampling; the
required ADC conversion time is 8 and 1/2 GPCLK cycles.
A total of 14.5 GPCLK cycles are used.
Table 8. Maximum Conversion Time
GPADC_MODE[7:6]
Units
00
01
10
11
TCXO frequency
MHz
19.68
19.68
19.68
19.68
Divide ratio
16
32
48
64
Conversion time
us, max
11.79
23.58
35.37
47.17
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