參數(shù)資料
型號： S1D2511B01-A0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù)： 23/34頁
文件大?。?/td> 330K
代理商： S1D2511B01-A0
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01
23
Read Mode
During read mode the second byte transmits the reply information.
The reply byte contains horizontal and vertical lock/unlock status, Xray activated or not, the horizontal and vertical
polarity detection. It also contains synchro detection status that is useful for
μ
P to assign sync priority.
A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and
SCL) to high impedance.
See I
2
C subaddress and control tables.
Sync processor
The internal sync processor allows the S1D2511B01 to accept any kind of input synchro signals:
- separated horizontal & vertical TTL-compatible sync signals,
- composite horizontal & vertical TTL-compatible sync signals.
Sync identification Status
The MCU can read (address read mode : 8D) the status register via the I
2
C bus, and then select the sync priority
depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and(when 12V is sup-
plied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only
5V is supplied.
In order to choose the right sync priority the MCU may proceed as follows(see I
2
C Address Table):
- refresh the status register,
- wait at least for 20ms(MAX. vertical period),
- read this status register,
Sync priotity choice should be:
Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present
and that no sync change occured.
Sync processor is also giving sync polarity information.
IC status
The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the Xary protection
(activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or directly
resetting it via the I
2
C interface.
Sync Inputs
Both H/HVin and Vsyncin inputs are TTL compatible trigger with hysterisis to avoid erratic detection.
Both inputs include a pull up register connected to V
DD
.
Sync Processor Output
The sync processr indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status regiser is set to 0. This information is mainly used to trigger safety procedures(like reducing B+ value) as
soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure for
Vext det
H/V det
V det
Sync priority subaddress 03 (D8)
Comment sync type
No
Yes
Yes
1
Separated H & V
Yes
Yes
No
0
Composite TTL H & V
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