參數(shù)資料
型號(hào): S1C60N05D0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, UUC53
封裝: DIE-53
文件頁數(shù): 28/95頁
文件大?。?/td> 736K
代理商: S1C60N05D0A0100
37
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 9-1.
Timing of pin change interrupts
9.3
Register Description
9.3.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The
value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last lon-
ger than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D
Q
LE
pcint_setflag
PCIF
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
Bit
765
432
10
ISC01
ISC00
EICRA
Read/Write
RR
RRR
R
R/W
Initial Value
000
00
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