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參數資料
| 型號： | S1C33E07B |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PBGA180 |
| 封裝： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-180 |
| 文件頁數： | 85/1018頁 |
| 文件大小： | 6970K |
| 代理商： | S1C33E07B |
II BUS MODULES: HIGH-SPEED DMA (HSDMA)
II-1-12
EPSON
S1C33E07 TECHNICAL MANUAL
Block length
When using block transfer mode (DxMOD[1:0] (D[15:14]/0x30112A + 0x10x) = 10), the data block length (in
units of the selected transfer data size) should be set using BLKLENx[7:0] (D[7:0]/0x301120 + 0x10x).
BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register
(D[7:0]/0x301120 + 0x10x)
In single transfer and successive transfer modes, BLKLENx[7:0] (D[7:0]/0x301120 + 0x10x) are used as bits 7
–0 of the transfer counter.
Note: When performing data transfer in block transfer mode, the block size must not be set to 0.
Transfer counter
Block transfer mode
In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] (D[15:8]/0x301120 +
0x10x) and TCx_H[7:0] (D[7:0]/0x301122 + 0x10x).
TCx_L[7:0]: Ch.x Transfer Counter [7:0] Bits in the HSDMA Ch.x Transfer Counter Register
(D[15:8]/0x301120 + 0x10x)
TCx_H[7:0]: Ch.x Transfer Counter [15:8] Bits in the HSDMA Ch.x Control Register
(D[7:0]/0x301122 + 0x10x)
Single transfer and successive transfer modes
In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using
BLKLENx[7:0] (D[7:0]/0x301120 + 0x10x), TCx_L[7:0] (D[15:8]/0x301120 + 0x10x) and TCx_H[7:0]
(D[7:0]/0x301122 + 0x10x).
Memory address
Standard mode (HSDMAADV (D0/0x30119C) = 0, default)
In standard mode, SxADRL[15:0] (D[15:0]/0x301124 + 0x10x) and SxADRH[11:0] (D[11:0]/0x301126 +
0x10x) are used to specify a 28-bit memory address.
SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register
(D[15:0]/0x301124 + 0x10x)
SxADRH[11:0]: Ch.x Source Address[27:16] in the HSDMA Ch.x High-Order Source Address Setup
Register (D[11:0]/0x301126 + 0x10x)
Advanced mode (HSDMAADV (D0/0x30119C) = 1)
In advanced mode, SxADRL[15:0] (D[15:0]/0x301164 + 0x10x) and SxADRH[15:0] (D[15:0]/0x301166 +
0x10x) are used to specify a 32-bit memory address.
SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register
for ADV mode (D[15:0]/0x301164 + 0x10x)
SxADRH[15:0]: Ch.x Source Address[31:16] in the HSDMA Ch.x High-Order Source Address Setup
Register for ADV mode (D[15:0]/0x301166 + 0x10x)
Note: In advanced mode, be sure to use the control registers for advanced mode to set a memory ad-
dress.
In single-address mode, data transfer is performed between the memory connected to the system interface and
an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to
specify an address. DxADRL[15:0] (D[15:0]/0x301168 + 0x10x) and DxADRH[15:0] (D[11:0]/0x30116A +
0x10x) are not used in single-address mode.
Address increment/decrement control
Standard mode (HSDMAADV (D0/0x30119C) = 0, default)
The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0]
(D[13:12]/0x301126 + 0x10x) is used to set this function.
SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup
Register (D[13:12]/0x301126 + 0x10x)
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