參數(shù)資料
型號: S19204
廠商: Applied Micro Circuits Corp.
英文描述: STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC
中文描述: 號STS - 192的SONET / SDH /前向糾錯/以太網(wǎng)/功能界別的16位與EDC的收發(fā)器
文件頁數(shù): 2/2頁
文件大?。?/td> 92K
代理商: S19204
S19250
SPECIFICATIONS
6290 Sequence Dr.
San Diego, CA 92121
P 858 450 9333
F 858 450 9885
www.amcc.com
For technical support, please call 1-800-840-6055 or 858-535-6517, or email support@amcc.com.
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and
conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions
and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify,
before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does
it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR
OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation. PowerPC and the PowerPC logo are registered trademarks of IBM Corporation. All other trademarks are the
property of their respective holders. Copyright 2006 Applied Micro Circuits Corporation. All Rights Reserved.
S19250_PB2011_v1.03_20061031
The sequence of operations is as follows:
Transmitter Operations
16-bit parallel input
Parallel-to-serial conversion
Serial data output
Receiver Operations
Serial input to limiting post-amp
Inter Symbol Interference (ISI) compensation
Threshold adjustment
Clock and Data recovery
Phase adjustment for improved BER
Serial-to-parallel conversion
16-bit parallel data and clock output
Figure 1. Mid-Plane Application Block Diagram
Figure 2. XFP Application Block Diagram
AMCC
S19250
16
ASIC
16
M
I
D
P
L
A
N
E
16
AMCC
S19250
16
ASIC
MDIO
MDIO
Enable Adaptive ISI Mitigation
Enable Adaptive Post-Amplifier Offset Control
Compensates up to 24" of FR-4
AMCC
S19250
16
ASIC
OR
FRAMER
OR
FEC
16
MDIO
Compensates up to 24" of FR-4
(Improves BER Performance and extends the reach of the standard XFP Module)
XFP MODULE
Enable Adaptive ISI Mitigation
Enable Adaptive Post-Amplifier Offset Control
Disable EDC
相關(guān)PDF資料
PDF描述
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S19250 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC
S19205 STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock
S19252 STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock
S19235 OC-192 SONET/SDH/FEC/GbE 16-bit Transceiver
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