參數(shù)資料
型號: S10077
廠商: Hamamatsu Photonics
英文描述: CMOS linear image sensor Digital output, built-in 8/10-bit AD converter, single power supply operation
中文描述: 線性圖像傳感器的CMOS數(shù)字輸出,內(nèi)置10位AD轉(zhuǎn)換器,單電源操作
文件頁數(shù): 3/5頁
文件大?。?/td> 120K
代理商: S10077
CMOS linear image sensor
S10077
3
I
AD converter specifications (Ta=25 °C)
Parameter
Digital output format
Symbol
-
Specification
Serial output
10
8
0 to 3.3
0 to 2.2
Unit
-
10-bit mode
8-bit mode
Vdd=5 V
Vdd=3.3 V
Resolution *
9
RESO
bit
Conversion voltage
range *
10
*9: Vsel=5 V (10-bit mode), 0 V (8-bit mode)
*10: Digital output is available from MSB as serial output.
10-bit mode: D9 to D0
8-bit mode: D7 to D0
-
V
I
Timing chart
Parameter
Symbol
Min.
0
12339
45
6000
0
Typ.
20
-
-
-
20
Max.
30
120000
-
-
30
Unit
ns
CLK
CLK
CLK
ns
Clock pulse rise and fall time
Start pulse time cycle
Start pulse low time
Start pulse high time *
11
Start pulse rise and fall time
*11: Signal charge integration time equals the High period of start pulse + 7 CLK cycles.
The shift register operation starts at the rise of CLK pulse immediately after ST pulse sets to low.
Integration time can be changed by changing the High-to-Low ratio of ST pulses.
tr (CLK), tf (CLK)
T2 (ST)
T3 (ST)
T4 (ST)
tr (ST), tf (ST)
012345
10
7
15
20
25
34.5
33
45
57
41.5 46.5
53.5
22
AO1
34
33
34
42
46
54
45
57
21
AO2
46
AO3
AO4
30
35
40
45
50
55
CLK
ST
EOS
AO
Trig (A)
DO
Trig (D)
EOC
T3 (ST)
T4 (ST)
T2 (ST)
DO1
DO2
T1 (CLK)
8-bit mode
G
In the neighborhood of start pixel
G
In the neighborhood of last pixel
CLK
ST
tf (CLK)
tr (CLK)
T1 (CLK)
tf (ST)
tr (ST)
KMPDC0224EA
12322
12281.5 12286.5 12293.5 12298.5 12305.5 12310.5
12317.5
12285
12297
12309
12320
12286
AO1023
12285
12297
1D0
1D7
1D0
1D7
1D0
1D7
1D0
CLK
ST
EOS
AO
Trig (A)
DO
Trig (D)
EOC
T4 (ST)
T2 (ST)
12298
AO1024
DO1022
DO1023
DO1024
KMPDC0225EA
Note) When using analog output AO, read the AO output at the falling edge of Trig (A).
When using digital output DO, read the DO output at the falling edge of Trig (D).
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