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參數(shù)資料
| 型號： | S-8204BAL-TCT1U |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | HALOGEN FREE AND LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 756K |
| 代理商： | S-8204BAL-TCT1U |
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BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.2_00
S-8204B Series
Seiko Instruments Inc.
11
3. 7 CIT pin Detection Voltage (VCIT)
The CIT pin detection voltage (VCIT) is the voltage at the CIT pin when the DOP pin’s voltage is set to “L” (voltage
VDS
× 0.1 V or less) after increasing the CIT pin’s voltage gradually, after setting VVINI = VDIOV1 max. + 0.05 V from
the initial state.
3. 8 Short circuit Detection Voltage Delay Time (tSHORT)
Short circuit detection voltage delay time (tSHORT) is a period in which the VINI pin’s voltage changes from “H” to
“L” by changing the VINI pin’s voltage instantaneously from the initial status to VSHORT max.+0.05 V.
4. Voltage for Start Charging 0 V Battery, Battery Voltage for Inhibit Charging 0 V Battery (Test
circuit 2)
Confirm both COP and DOP pins are in “H” (its voltage level is VDS
× 0.9 V or more) after setting VVMP = VSEL =
VCTLC = VCTLD = VDD, VVINI = VSS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2 = V3 = V4 = 3.5 V.
(This status is referred to as initial status.)
According to user’s selection of the function to charge 0 V battery, either function of Voltage for start charging 0 V
battery or Battery voltage for inhibit charging 0 V battery is applied to each product.
4. 1 Voltage for Start Charging 0 V Battery (V0CHA) (Product with function to charge 0 V battery)
Voltage for start charging 0 V battery (V0CHA) is a voltage at V1; when a voltage at the COP pin is set to “H” after
increasing a voltage at V1 gradually, after setting V1 = V2 = V3 = V4 = 0 V from the initial status.
4. 2 Battery Voltage for Inhibit Charging 0 V Battery (V0INH) (Product with function to inhibit charging 0 V
battery)
Battery voltage for inhibit charging 0 V battery (V0INH) is a voltage at V1; when a voltage at the COP pin is set to
“L” after decreasing a voltage at V1 gradually from the initial status.
5. Resistance between VMP and VDD, Resistance between VMP and VSS, VC1 Pin Current, VC2 Pin
Current, VC3 Pin Current, VC4 Pin Current, CTLC Pin Current “H”, CTLC Pin Current “L”, CTLD
Pin Current “H”, CTLD Pin Current “L”, SEL Pin Current “H”, SEL Pin Current “L”, COP Pin
Source Current, COP Pin Leakage Current, DOP Pin Source Current, DOP Pin Sink Current
(Test circuit 4)
Set VCTLC = VCTLD = VVMP = VSEL = VDD, VVINI = VSS, V1 = V2 = V3 = V4 = 3.5 V, set other pins open. (This status is
referred to as initial status.)
5. 1 Resistance between VMP and VDD (RVMD)
The value of resistance between VMP and VDD (RVMD) can be defined by RVMD = VDS/IVMD by using the VMP pin’s
current (IVMD) when VVINI = 1.5 V and VVMP = VSS after the initial status.
5. 2 Resistance between VMP and VSS (RVMS)
The value of resistance between VMP and VSS (RVMS) can be defined by RVMS = VDS/IVMS by using the VMP pin’s
current (IVMS) when V1 = V2 = V3 = V4 = 1.8 V after the initial status.
5. 3 VC1 Pin Current (IVC1), VC2 Pin Current (IVC2), VC3 Pin Current (IVC3), VC4 Pin Current (IVC4)
In the initial status, each current flows in the VC1 pin, VC2 pin, VC3 pin, VC4 pin is the VC1 pin current (IVC1), the
VC2 pin current (IVC2), the VC3 pin current (IVC3), the VC4 pin current (IVC4), respectively.
5. 4 CTLC Pin Current “H” (ICTLCH), CTLC Pin Current “L” (ICTLCL)
In the initial status, a current which flows in the CTLC pin is the CTLC pin current “H” (ICTLCH). After that,
decreasing a voltage at the CTLC pin gradually, the maximum current which flows in the CTLC pin is; the CTLC
pin current “L” (ICTLCL).
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