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參數(shù)資料
| 型號： | S-4525BA |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Dot Matrix LCD Driver(點陣LCD驅(qū)動器) |
| 中文描述： | 點陣LCD驅(qū)動器（點陣液晶驅(qū)動器） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 166K |
| 代理商： | S-4525BA |
DOT MATRIX LCD DRIVER
S-4525BA
8
Seiko Instruments Inc.
10. Page address
The display RAM is composed of four pages. When accessing the display data RAM from MPU, the page of the
display data RAM is set a command.
11. CR oscillation circuit
This
is a CR oscillation sircuit for generating adisplay closk.
Oscillation frequency is approximately 18 kHz
at Rf 1 M
.
12. LCD drive circuit
The S-4525BA has a 16 common and a 61 segment driver output. An LCD drive waveform which is a two-
frame AC drive method (B) type is generated. Refer to Figure 7, LCD drive waveform.
13. Display timing circuit
The display timing is generated by the clock using a CR oscillation circuit or an external clock, and a frame
signal FR.
When configuring an LCD panel with more than two S-4525BA, the S-4525BA on the slave side syncronizes to
the falling of FR signal. So, on the slave side of the S-4525BA, the LCD drive waveform is synchronized only by
input of the FR signal on the master side. As shown in Figure 8, the display drive output on the slave side, after
the common output COM15 on master side, is executed in COM16 through COM31. The FR signals are that of
the duty 50 % of synchronized to the COM output timing.
14. Line address
This is the address for reading the LCD RAM data to the LCD data latch. The line address is incremented
synchronizing with the common output. The display start line is set with a command.
15. Display data latch
The display data latch is the circuit for latching one line’s display data from the display RAM. The display data is
output from this latch to the LCD drive circuit. Since the display ON/OFF and the display all-lit ON/OFF control
the display data latch, it has no effect on the display RAM data.
16. Master/Slave selection
Master and slave selection is executed through the master/slave terminal logic. The Master IC and the Slave IC
have different terminal functions.
Note 1
CR oscillation circuit: In slave operation, OSC
1
is at high impedance. OSC
2
is connected to OSC
2
on the
master side as a display clock input terminal.
Common output:
Master operation is output counterclockwise from terminal No.96 to No.11.
Slave operation is output clockwise from terminal No.11 to No.96.
Note 2
Product name
M/S
V
DD
V
SS
FR
COM output
COM
0
to COM
15
COM
31
to COM
16
OSC
1
Input
NC
OSC
2
Output
Input
Master
Slave
Output
Input
Table 12
S-4525BA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-4525BACA | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:DOT MATRIX LCD DRIVER |
| S-4525BACG | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:DOT MATRIX LCD DRIVER |
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