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參數資料
| 型號： | S-3531A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | CMOS Real-Time Clock IC Supporting an IIC-Bus(支持IIC-BUS的CMOS實時時鐘芯片) |
| 中文描述： | CMOS實時時鐘IC支持一個IIC總線（支持IIC總線的實時時鐘芯片的CMOS） |
| 文件頁數： | 16/31頁 |
| 文件大?。?/td> | 185K |
| 代理商： | S-3531A |
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REAL-TIME CLOCK
S-3531A
Seiko Instruments Inc.
15
6.Power voltage detecting circuit
S-3531A has an internal power voltage detecting circuit. This circuit gives sampling movement for only 15.6msec. once a
second.
If the power voltage decreases below the detected voltage (VDET), sampling movement stops. Only when subsequent
communication is of the status read command, the output of the latch circuit is transferred to the sift register and the
sampling movement is resumed.
Decrease in power voltage can be monitored by reading the POWER flag.
That is to say, once decrease in power voltage is detected, any detecting operation is not performed and "H" is held unless
you perform initialization or send the status read command.
[Note]
When power voltage is increased and the first read operation is performed after decrease in power voltage occurs and the
latch circuit latches "H", "1" can be read on the POWER flag. However, if the next read operation is performed after the
sampling of the detecting circuit, the POWER flag is reset since sampling is subsequently allowed. See the timing diagram
below.
Latch circuit output
Sampling pulse
(0)
1sec
1sec
Stop
Stop
Stop
(1)
(1)
(1)(1)
(1) (1)
(0)
VDD
POWER flag
V
DET
Communication
Latch circuit
output
Sampling pulse
Carry pulse
1sec
1sec
(1)
(0)
Communication
POWER flag
[Timing of sampling pulse]
0.5sec
0.5sec
7.8msec
Carry-up timing
15.6msec
Latch timing
1 Hz
V
DET
Sampling pulse
(1)
(0)
Figure 16 Timing of the power voltage detecting circuit
VDD
Stop
Stop
Stop
Stop
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