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參數資料
| 型號： | S-29690A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 32Kbit Serial EEPROM(32K位串行EEPROM) |
| 中文描述： | 32Kbit串行EEPROM（32K的位串行EEPROM的） |
| 文件頁數： | 9/43頁 |
| 文件大?。?/td> | 167K |
| 代理商： | S-29690A |
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CMOS SERIAL E
2
PROM
S-29590A / 29690A
8
3.
Write enable (PEN) and Write disable (PDS)
The PEN instruction puts the S-29590A / 690A series into write enable mode, which accepts PROGRAM instructions.
The PDS instruction puts the S-29590A / 690A series into write disable mode, which refuses PROGRAM instructions.
The S-29590A / 690A series powers on in write disable mode, which protects data against unexpected, erroneous write
operations caused by noise and/or CPU malfunctions. It should be kept in write disable mode except when performing
write operations.
11=PEN
00=PDS
0
0
X
1
2
3
4
5
6
7
8
DI
CS
SK
X
X
16
X
Figure 6
PEN/PDS Timing (S-29690A)
Receiving a Start-Bit
A start bit can be recognized by latching the high level of DI at the rising edge of SK after changing CS to high (Start-bit
Recognition). The write operation begins by inputting the write instruction and setting CS to low. The DO pin then outputs
low during the write operation and high at its completion by setting CS to high (Verify Operation). Therefore, only after a
write operation, in order to accept the next command by having CS go high, the DO pin switch from a state of high-
impedence to a state of data output; but if it recognizes a start-bit, the DO pin returns to a state of high-impedence (see
Figure 3).
Three-wire Interface (DI-DO direct connection)
Although the normal configuration of a serial interface is a 4-wire interface to CS, SK, DI, and DO, a 3-wire interface is
also a possibility by connecting DI and DO. However, since there is a possibility that the DO output from the serial memory
IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between DI and DO in order to
give preference to data output from the CPU to DI(See Figure 7).
DI
DO
SIO
Figure 7
CPU
S-29590A / 29690A
R : 10 to 100 k
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