參數(shù)資料
型號: S-29291A
廠商: Seiko Instruments Inc.
英文描述: 128-Word x 16-Bit CMOS Serial EEPROM(2K位CMOS串行EEPROM)
中文描述: 128字× 16位的CMOS串行EEPROM(2K位的CMOS串行EEPROM的)
文件頁數(shù): 7/44頁
文件大小: 213K
代理商: S-29291A
CMOS SERIAL E
2
PROM
S-29X91A Series
6
Seiko Instruments Inc.
Operation
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched at the rising edge of
SK after changing CS to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses
after CS goes high. Instruction finishes when CS goes low, where it must be low between commands during t
CDS
.
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode. The start bit + instruction,
address, and data are 8-bit instructions. This makes it easy to prepare your own software using a serial interface
incorporated into the CPU.
1. READ
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, 16-bit data is
continuously output in synchronization with the falling edge of SK.
When all of the data (D
15
to D
0
) in the specified address has been read, the data in the next address can be read with
the input of another SK clock. Thus, the data over whole area of the memory can be read by continuously inputting
SK clocks as long as CS is high.
The last address (An
A1 A0 = 1
11) rolls over to the top address (An
A1 A0 = 0
00).
Figure 5 Read Timing (S-29391A)
*
On the S-29191A, A
7
and A
6
are optional.
On the S-29291A, A
7
is optional.
A
0
A
6
17
50
34
19
D
15
D
15
D
14
D
14
D
13
D
14
Hi
-
Z
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+1
D
13
D
0
D
1
D
2
D
15
Hi-Z
A
1
A
2
A
3
A
4
A
5
A
7
0
1
33
32
31
30
29
16
15
9
3
2
1
49
48
47
46
45
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+2
D
13
D
0
D
1
D
2
18
CS
SK
DI
DO
8
7
6
5
4
12
14
11
10
13
X
X
X
0
0
* *
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