參數(shù)資料
型號(hào): S-1121B44MC-N3D-TFG
元件分類(lèi): 固定正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器
英文描述: 4.4 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
封裝: LEAD FREE, SOT-23, 5 PIN
文件頁(yè)數(shù): 6/25頁(yè)
文件大?。?/td> 265K
代理商: S-1121B44MC-N3D-TFG
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1111/1121 Series
Rev.5.0_00
Seiko Instruments Inc.
14
Operation
1. Basic operation
Figure 11 shows the block diagram of the S-1111/1121 Series.
The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-
divided by feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
Reference voltage
circuit
VOUT
*1
*1.
Parasitic diode
VSS
VIN
Rs
Rf
Error
amplifier
Current
supply
Vref
+
Vfb
Figure 11
2. Output transistor
The S-1111/1121 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
相關(guān)PDF資料
PDF描述
S-1121B21MC-N2G-TFG 2.1 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PDSO5
S-1121B26MC-N2L-TFG 2.6 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PDSO5
S-1121B17MC-N2C-TFG 1.7 V FIXED POSITIVE LDO REGULATOR, 1.4 V DROPOUT, PDSO5
S-1121B33MC-N2S-TFG 3.3 V FIXED POSITIVE LDO REGULATOR, 0.3 V DROPOUT, PDSO5
S-1121B54MC-N3NTFG 5.4 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
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