參數(shù)資料
型號(hào)： S-1121B39MC-N2Y-TFG
元件分類(lèi)： 固定正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器
英文描述： 3.9 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
封裝： LEAD FREE, SOT-23, 5 PIN
文件頁(yè)數(shù)： 8/25頁(yè)
文件大小： 265K
代理商： S-1121B39MC-N2Y-TFG
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1111/1121 Series
Rev.5.0_00
Seiko Instruments Inc.
16
Precautions
Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low.
When mounting an output capacitor between the VOUT and VSS pins (CL) and a capacitor for stabilizing
the input between VIN and VSS pins (CIN), the distance from the capacitors to these pins should be as
short as possible.
Note that the output voltage may increase when a series regulator is used at low load current (1.0 mA or
less).
This IC performs phase compensation by using an internal phase compensator and the ESR of an
output capacitor. Therefore, always place a capacitor of 2.2
μF or more between VOUT and VSS pins.
A tantalum type capacitor is recommended. Moreover, to secure stable operation of the S-1111/1121
Series, it is necessary to employ a capacitor with an ESR within an optimum range (0.5 to 5
Ω). Using a
capacitor whose ESR is outside the optimum range (approximately 0.5 to 5
Ω), whether larger or
smaller, may cause an unstable output, resulting in oscillation. Perform sufficient evaluation under the
actual usage conditions for selection, including evaluation of temperature characteristics.
The voltage regulator may oscillate when the impedance of the power supply is high and the input
capacitor is small or an input capacitor is not connected.
The application conditions for the input voltage, output voltage, and load current should not exceed the
package power dissipation.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
In determining the output current, attention should be paid to the output current value specified in Table
6 in the electrical characteristics and footnote *5 of the table.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
相關(guān)PDF資料
PDF描述
S-1121B48MC-N3H-TFG 4.8 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
S-1121B20MC-N2F-TFG 2 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PDSO5
S-1121B25MC-N2K-TFG 2.5 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PDSO5
S-1121B16MC-N2B-TFG 1.6 V FIXED POSITIVE LDO REGULATOR, 1.4 V DROPOUT, PDSO5
S-1121B50MC-N3J-TFG 5 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S-1121B40MC-N2ZTFG 制造商:Seiko Instruments Inc (SII) 功能描述:
S-1121B41MC-N3ATFG 制造商:Seiko Instruments Inc (SII) 功能描述:LINEAR LDO REG HI 50UA IQ 150MA IOUT
S-1121B42MC-N3BTFG 制造商:SII 制造商全稱(chēng):Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT
S-1121B43MC-N3CTFG 制造商:Seiko Instruments Inc (SII) 功能描述:LINEAR LDO REG HI 50UA IQ 150MA IOUT
S-1121B44MC-N3DTFG 制造商:SII 制造商全稱(chēng):Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT
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