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參數(shù)資料
| 型號： | S-1121B32MC-N2R-TFG |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 3.2 V FIXED POSITIVE LDO REGULATOR, 0.3 V DROPOUT, PDSO5 |
| 封裝： | LEAD FREE, SOT-23, 5 PIN |
| 文件頁數(shù)： | 7/25頁 |
| 文件大小： | 265K |
| 代理商： | S-1121B32MC-N2R-TFG |
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1111/1121 Series
Seiko Instruments Inc.
15
3. Shutdown pin (ON/OFF pin)
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-
in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially
reduce the current consumption. The VOUT pin becomes the VSS level due to the internally divided
resistance of several hundreds k
Ω between the VOUT pin and VSS pin.
The structure of the ON/OFF pin is as shown in Figure 12. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption
increases if a voltage of 0.3 V to VIN – 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not
used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.
Table 7
Logic Type
ON/OFF Pin
Internal Circuits
VOUT Pin Voltage
Current Consumption
A
“L”: Power on
Operating
Set value
ISS1
A
“H”: Power off
Stopped
VSS level
ISS2
B
“L”: Power off
Stopped
VSS level
ISS2
B
“H”: Power on
Operating
Set value
ISS1
VSS
ON/OFF
VIN
Figure 12
Selection of Output Capacitor (CL)
The S-1111/1121 Series performs phase compensation using the internal phase compensator in the IC and the
ESR (Equivalent Series Resistance) of the output capacitor to enable stable operation independent of changes
in the output load. Therefore, always place a capacitor (CL) of 2.2 μF or more between VOUT and VSS pins.
For stable operation of the S-1111/1121 Series, it is essential to employ a capacitor whose ESR is within an
optimum range.
Using a capacitor whose ESR is outside the optimum range (approximately 0.5 to 5
Ω),
whether larger or smaller, may cause an unstable output, resulting in oscillation. For this reason, a tantalum
electrolytic capacitor is recommended.
When a ceramic capacitor or an OS capacitor with a low ESR is used, it is necessary to connect an additional
resistor that serves as the ESR in series with the output capacitor.
The required resistance value is
approximately 0.5 to 5
Ω, which varies depending on the usage conditions, so perform sufficient evaluation for
selection. Ordinarily, around 1.0
Ω is recommended.
Note that an aluminum electrolytic capacitor may increase the ESR at a low temperature, causing oscillation.
When using this kind of capacitor, perform thorough evaluation, including evaluation of temperature
characteristics.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-1121B33MC-N2S-TF | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3 Volt 1% 0.2mV RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| S-1121B33MC-N2STFG | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3 Volt 1% 0.2mV RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| S-1121B33PN-N2S-TF | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3 Volt 1% 0.2mV RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| S-1121B33PN-N2STFG | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3 Volt 1% 0.2mV RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| S-1121B34MC-N2TTFG | 制造商:Seiko Instruments Inc (SII) 功能描述:LDO Voltage Regulators LINEAR LDO REG HI 50UA IQ 150MA IOUT |
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