參數(shù)資料
型號(hào): S-1009N32I-N4T1U
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4
封裝: HALOGEN AND LEAD FREE, SC-82AB, 4 PIN
文件頁數(shù): 5/38頁
文件大?。?/td> 493K
代理商: S-1009N32I-N4T1U
SUPER-LOW CURRENT CONSUMPTION SUPER HIGH-ACCURACY VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
Rev.4.2_00
S-1009 Series
Seiko Instruments Inc.
13
2. Delay Circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power voltage (VDD) exceeds
the release voltage (
+VDET) when VDD is turned on. The output signal is not delayed when VDD decreases to the
detection voltage (
VDET) or less (Refer to Figure 14).
The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached external capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following
equation.
tD [ms] = Delay coefficient
× CD [nF] + tD0 [ms]
Delay coefficient (
+85°C) : Min. 2.82, Typ. 4.20, Max. 5.72
Delay coefficient (
+25°C) : Min. 4.70, Typ. 5.47, Max. 6.24
Delay coefficient (
40°C) : Min. 5.64, Typ. 8.40, Max. 12.01
tD0 (
40°C to +85°C) : Min. 0.01 ms, Typ. 0.10 ms, Max. 0.24 ms
When the CD value is sufficiently large, the tD0 value can be disregarded.
Caution 1.
When the CD pin is open, a double pulse shown in Figure 15 may appear at release.
To avoid the double pulse, attach 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
VOUT
Time
Figure 15
2.
Print circuit board layout should be made in such a way that no current flows into or flows
from the CD pin since the impedance of the CD pin is high, otherwise correct delay time
cannot be provided.
3.
There is no limit for the capacitance of the external capacitor (CD) as long as the leakage
current of the capacitor can be ignored against the built-in constant current value. Leakage
current causes deviation in delay time. When the leakage current is larger than the built-in
constant current, no release takes place.
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