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參數(shù)資料
| 型號(hào)： | RX5501 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | RX5501 |
for the low-pass filter is also affected by the threshold level setting of
DS1. The bandwidth must be increased as the threshold is in-
creased to minimize data pulse-width variations with signal ampli-
tude.
Receiver Pulse Generator and RF Amplifier Bias
The receiver amplifier-sequence operation is controlled by the Pulse
Generator & RF Amplifier Bias module, which in turn is controlled by
the PRATE and PWIDTH input pins, and the Power Down (sleep)
Control Signal from the Bias Control function.
In the low data rate mode, the interval between the falling edge of
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse
t
PRI
is set by a resistor between the PRATE pin and ground. The in-
terval can be adjusted between 0.1 and 5 μs. In the high data rate
mode (selected at the PWIDTH pin) the receiver RF amplifiers oper-
ate at a nominal 50%-50% duty cycle. In this case, the start-to-start
period t
PRC
for ON pulses to RFA1 are controlled by the PRATE re-
sistor over a range of 0.1 to 1.1 μs.
In the low data rate mode, the PWIDTH pin sets the width of the ON
pulse t
PW1
to RFA1 with a resistor to ground (the ON pulse width
t
PW2
to RFA2 is set at 1.1 times the pulse width to RFA1 in the low
data rate mode). The ON pulse width t
PW1
can be adjusted between
0.55 and 1 μs. However, when the PWIDTH pin is connected to Vcc
through a 1 M resistor, the RF amplifiers operate at a nominal
50%-50% duty cycle, facilitating high data rate operation. In this
case, the RF amplifiers are controlled by the PRATE resistor as de-
scribed above.
Both receiver RF amplifiers are turned off by the Power Down Con-
trol Signal, which is invoked in the sleep mode.
Receiver Mode Control
The receiver operating modes – receive and power-down (sleep),
are controlled by the Bias Control function, and are selected with the
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
both high place the unit in the receive mode. Setting CNTRL1 and
CNTRL0 both low place the unit in the power-down (sleep) mode.
CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs
must be held at a logic level; they cannot be left unconnected. At
turn on, the voltages on CNTRL1 and CNTRL0 should rise with Vcc.
Receiver Event Timing
Receiver event timing is summarized in Table 1. Please refer to this
table for the following discussions.
Turn-On Timing
The maximum time t
PR
required for the receive function to become
operational at turn on is influenced by two factors. All receiver cir-
cuitry will be operational 5 ms after the supply voltage reaches
2.7 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabi-
lized in 3 time constants (3*t
BBC
). The total turn-on time to stable re-
ceiver operation for a 10 ms power supply rise time is:
t
PR
= 15 ms + 3*t
BBC
The voltage on CNTRL1 and CNTRL0 should rise with Vcc until it
reaches 2.7 Vdc. Thereafter, the power down (sleep) mode may be
invoked.
Sleep and Wake-Up Timing
The maximum transition time from the receive mode to the
power-down (sleep) mode t
RS
is 10 μs after CNTRL1 and CNTRL0
are both low (1 μs fall time).
The maximum transition time t
SR
from the sleep mode to the receive
mode is 3*t
BBC
, where t
BBC
is the BBOUT-CMPIN coupling-capacitor
time constant. When the operating temperature is limited to 60
o
C,
the time required to switch from sleep to receive is dramatically less
for short sleep times, as less charge leaks away from the BBOUT-
CMPIN coupling capacitor.
Pulse Generator Timing
In the low data rate mode, the interval t
PRI
between the falling edge
of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor R
PR
be-
tween the PRATE pin and ground. The interval can be adjusted be-
tween 0.1 and 5 μs with a resistor in the range of 51 K to 2000 K.
The value of the R
PR
is given by:
R
PR
= 404* t
PRI
+ 10.5, where t
PRI
is in μs, and R
PR
is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the re-
ceiver RF amplifiers operate at a nominal 50%-50% duty cycle. In
this case, the period t
PRC
from the start of an ON pulse to the first
RF amplifier to the start of the next ON pulse to the first RF amplifier
is controlled by the PRATE resistor over a range of 0.1 to 1.1 μs us-
ing a resistor of 11 K to 220 K. In this case R
PR
is given by:
R
PR
= 198* t
PRC
- 8.51, where t
PRC
is in μs and R
PR
is in kilohms
In the low data rate mode, the PWIDTH pin sets the width of the ON
pulse to the first RF amplifier t
PW1
with a resistor R
PW
to ground (the
ON pulse width to the second RF amplifier t
PW2
is set at 1.1 times
the pulse width to the first RF amplifier in the low data rate mode).
The ON pulse width t
PW1
can be adjusted between 0.55 and 1 μs
with a resistor value in the range of 200 K to 390 K. The value of
R
PW
is given by:
R
PW
= 404* t
PW1
- 18.6, where t
PW1
is in μs and R
PW
is in kilohms
However, when the PWIDTH pin is connected to Vcc through a 1 M
resistor, the RF amplifiers operate at a nominal 50%-50% duty cy-
cle, facilitating high data rate operation. In this case, the RF amplifi-
ers are controlled by the PRATE resistor as described above.
LPF Group Delay
The low-pass filter group delay is a function of the filter 3 dB band-
width, which is set by a resistor R
LPF
to ground at the LPFADJ pin.
The minimum 3 dB bandwidth f
LPF
= 1445/R
LPF
, where f
LPF
is in kHz,
and R
LPF
is in kilohms.
The maximum group delay t
FGD
= 1750/f
LPF
= 1.21*R
LPF
, where t
FGD
is in μs, f
LPF
in kHz, and R
LPF
in kilohms.
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