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Real Time Clock Modules - Seiko Epson
Serial Interface RTC-4553 Continued
Register Table
MODE 0
MODE1
MODE 2
User RAM Domain 2
D
3
D
2
Address
A
3
A
2
A
1
A
0
Register
symbol
Counter control register
D
2
D
1
D
0
User RAM Domain 1
D
3
D
2
D
3
register name
D
1
D
0
D
1
D
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S
1
S
10
MI
1
MI
10
H
1
H
10
W
D
1
D
10
M0
1
M0
10
Y
1
Y
10
C
1
C
2
C
3
S
8
0
mi
8
0
h
8
S
4
S
40
mi
4
mi
40
h
4
0
w
4
d
4
0
mo
4
0
y
4
y
40
S
2
S
20
mi
2
mi
20
h
2
h
20
w
2
d
2
d
20
mo
2
0
y
2
y
20
S
1
S
10
mi
1
mi
10
h
1
h
10
w
1
d
1
d
10
mo
1
mo
1
y
1
y
10
1-second digit register
10-seconds digit register
1-minute digit register
10-minutes digit register
1-hour digit register
10-hours digit register
Day of the week digit register
1-day digit register
10-days digit register
1-month digit register
10-months digit register
1-year digit register
10-years digit register
Control register 1
Control register 2
Control register 3
RA
3
RA
7
RA
11
RA
15
RA
19
RA
23
RA
27
RA
31
RA
35
RA
39
RA
43
RA
47
RA
51
RA
55
RA
59
RA
2
RA
6
RA
10
RA
14
RA
18
RA
22
RA
26
RA
30
RA
34
RA
38
RA
42
RA
46
RA
50
RA
54
RA
58
RA
1
RA
5
RA
9
RA
13
RA
17
RA
21
RA
25
RA
29
RA
33
RA
37
RA
41
RA
45
RA
49
RA
53
RA
57
RA
0
RA
4
RA
8
RA
12
RA
16
RA
20
RA
24
RA
28
RA
32
RA
36
RA
40
RA
44
RA
48
RA
52
RA
56
RA
63
RA
67
RA
71
RA
75
RA
79
RA
83
RA
87
RA
91
RA
95
RA
99
RA
103
RA
107
RA
111
RA
115
RA
119
RA
62
RA
66
RA
70
RA
74
RA
78
RA
82
RA
86
RA
90
RA
94
RA
98
RA
102
RA
106
RA
110
RA
114
RA
118
RA
61
RA
65
RA
69
RA
73
RA
77
RA
81
RA
85
RA
89
RA
93
RA
97
RA
101
RA
105
RA
109
RA
113
RA
117
RA
60
RA
64
RA
68
RA
72
RA
76
RA
80
RA
84
RA
88
RA
92
RA
96
RA
100
RA
104
RA
108
RA
112
RA
116
PM/AM
0
d
8
0
mo
8
0
y
8
y
80
TPS
30ADJ
CNTR
24/12
*
MS
0
BUSY
PONC
SYSR
TEST
MS
1
Same as mode 0
Same as mode 0
Timing Chart
Switching Characteristics
VDD=5V ±10%, GND=0V, Ta=-30 to 70°C)
Item
Symbol Condition Min Typ Max. Unit
SCK input frequency
SCK “L” time
SCK “H” time
SCK Pause time
CS
0
Set up time
CS
0
Hold time
S
IN
Data set up time
S
IN
Data hold time
WR Set up time
WR Hold time
S
OUT
Delay time
C
and C
Enable
to S
OUT
Output
CS
0
Disable
to S
OUT
High Z
CS
1
to S
OUT
Output
CS
1
Enable
to S
OUT
High Z
Block Diagram
fSCK
t
WSCKL
t
WSCKH
PS
t
SCS
t
HSC
t
SD
t
HD
t
SWR
t
HWR
t
DSO
500 kHz
1.0
1.0
1.0
0
0.5
0.2
0.2
1.0
0.5
μsec
CL=100pF
150
500
t
DSZ1
CL=100pF
100
t
DSZ2
CL=100pF
100
nsec
t
DPZ1
CL=100pF
100
t
DPZ2
CL=100pF
100