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參數(shù)資料
| 型號： | RTC-8593 |
| 元件分類： | XO, clock |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | SOP-14 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 231K |
| 代理商： | RTC-8593 |
72
Real time clock module
Switching characteristics
Block diagram
Register table
Timing chart
t SU: STA
t HD: STA
t SU: DAT
t SU: STO
t VD: DAT
t HD: DAT
t SUF
t TLH
t THL
t LOW
t HIGH
1/f SCL
SCL
Protocol
Start
Condition (s)
Bit 7
MSB (A7)
Bits
(A6)
SDA
SCL
SDA
OSC1
Cg=10 pF
RTC-8583
INT
VDD
GND1.2
AO
SCL
SDA
32.768 kHz
OSC1
Cg=10 pF
RTC-8593 Series
INT
VDD
GND
RESET
SCL
SDA
32.768 kHz
BITO
LSB (R/W)
ACK
(A)
STOP
Condition (p)
OSC
Divider
Register
Control
Logic
Address
Register
RAM
(8 x 240)
Power-ON
RESET
&
Counter
I C-BUS
Interface
2
OSC
Divider
Register
Control
Logic
Address
Register
&
Counter
RESET
I C-BUS
Interface
2
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10 to FF
Register name
CNT
1/100SEC
SEC
MIN
HOUR
DAY
MONTH
TIMER
ALARM
A-1/100
A-SEC
A-MIN
A-HR
A-DAY
A-MON
A-TIM
count
0 to 99
0 to 59
0 to 23
0 to 31
0 to 12
0 to 99
0 to 59
0 to 23
0 to 31
0 to 12
0 to 99
0 to FF
bit 7
STOP
8/10
10S8
10MIN8
12/24
YEAR2
W4
10TIMER8
AIE
A-8/10
10A-SEC8
10A-MIN8
A-12/24
10A-TIM8
bit 6
HOLD
4/10
10S4
10MIN4
AM/PM
YEAR1
W2
10TIMER4
TAIE
A-4/10
10A-SEC4
10A-MIN4
A-AM/PM
—
10A-TIM4
bit 5
MODE1
2/10
10S2
10MIN2
10HOUR2
10DAY2
W1
10TIMER2
AS1
A-2/10
10A-SEC2
10A-MIN2
10A-HR2
A-DAY2
10A-TIM2
bit 4
MODE2
1/10
10S1
10MIN1
10HOUR1
10DAY1
10MONTH1
10TIMER1
AS0
A-1/10
10A-SEC1
10A-MIN1
10A-HR1
A-DAY1
10A-MON1
10A-TIM1
bit 3
MASK
8/100
S8
MIN8
HOUR8
DAY8
MONTH8
TIMER8
TIE
A-8/100
10A-SEC8
10A-MIN8
A-HR8
A-DAY8
10A-MON8
A-TIM8
bit 2
ALM
4/100
S4
MIN4
HOUR4
DAY4
MONTH4
TIMER4
TCP2
A-4/100
10A-SEC4
10A-MIN4
A-HR4
A-DAY4
10A-MON4
A-TIM4
bit 1
AF
2/100
S2
MIN2
HOUR2
DAY2
MONTH2
TIMER2
TCP1
A-2/100
10A-SEC2
10A-MIN2
A-HR2
A-DAY2
10A-MON2
A-TIM2
bit 0
TF
1/100
S1
MIN1
HOUR1
DAY1
MONTH1
TIMER1
TCP0
A-1/100
10A-SEC1
10A-MIN1
A-HR1
A-DAY1
10A-MON1
A-TIM1
User's RAM (RTC-8583 is available)
Item
SCL clock frequency
Spike tolerance on bus
Bus free time
Start condition set-up time
Hold time
SCL “L” time
SCL “H” time
SCL, SDA rise time
SCL, SDA fall time
Date set-up time
Date hold time
SCL low to data out valid
Stop condition set-up time
Event counter frequency
Symbol
fSCL
tSW
tBUF
tSU; STA
tHD; STA
tLOW
tHIGH
tTLH
tTHL
tSU; DAT
tHD; DAT
tVD; DAT
tSU; STO
fi
Min.
—
4.7
4.0
4.7
4.0
—
250
0
—
4.0
—
Max.
100
—
1.0
0.3
—
3.4
—
1.0
Unit
kHz
ns
s
ns
s
MHz
—
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