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參數(shù)資料
| 型號(hào)： | RTC-58323 |
| 廠商： | 愛(ài)普生（中國(guó)）有限公司 |
| 英文描述： | 4-Bit I/ O Connection Real Time Clock Module(4位I/ O連接實(shí)時(shí)時(shí)鐘模塊) |
| 中文描述： | 4位I / O連接實(shí)時(shí)時(shí)鐘模塊（4位的I / O連接實(shí)時(shí)時(shí)鐘模塊） |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | RTC-58323 |
74
Real time clock module
Switching characteristics
Write & read mode
Supplement
Item
mark
24/12
PM/AM
Register table
CS
1
CS
2
t
CS
t
AS
t
AW
t
AH
t
DS
t
WW
t
DH
t
RI
t
RA
t
DD
DATA VALID
DATA INVALID
t
CH
ADDRESS
WRITE
D
0 -
D
3
Write and read timing
Date holding timing
4.5 V
4.5 V
2.2 to 4.5 V
Data holding mode
CS
2
or WR not occurred
CS
1
≤
0.8 V
0
μ
s Min.
0
μ
s Min.
t
CDR
t
R
V
IL
V
IL
V
IH2
V
IH2
CS
1
V
DD
Interface
possible with
the external
terminals
Interface
possible with
the external
terminals
WRITE
WRITE
READ
READ
DATA
(V
DD
=5 V
±
0.5 V Ta=+25
°
C)
DATA
ADDRESS
Block diagram
OSC
TRI-STATE
CONTROL
SWITCH
DATA BUS
1024 Hz
1/2
Reg
1/3600 Hz
ADDRESS
LATCH
D
BUSY
Reg
BUSY
STOP
TEST
READ
CS
1
R
P
Crystal oscillator circuit
32.768 kHz
R
P
R
P
R
P
R
P
R
P
R
P
CS
2
D
0
D
1
D
2
D
3
ADWRITE
WRITE
1/10
sec.
1/6
1/10
minute
1/6
1/10
day
1/3
1/10
year
1/10
1/12
month
1/12
hour
or
1/24
1/7
day
of
week
D
10
D
11
D
12
D
13
A
0
A
1
A
2
A
3
0
1
2
3
4
5
6
7
8
9
A
B
C
D
S1
S10
MI1
MI10
H
1
H
10
W
D1
D10
MO1
Y1
Y10
D
S1
1/60 Hz
S10
1 Hz
1 Hz
1024 Hz
MI1 M1
TEST
WRITE
H
10
H
1
10
W
D1
D10
MO1
MOI0
Y1
Y10
E to F
E to F
=200
k
(Typ.)
A
D
3
and D
2
of
10 days digit
Reset register
Standard
signal register
Description
Writable. Recognized as 0 while in read mode
“
1
”
=24 h mode,
“
0
”
=12 h mode
“
1
”
=PM,
“
0
”
=AM. In 24 h mode, this will be
“
0
”
Used to select leap year. Calculated according to the surplus
Calendar
Gregorian calendar
0
by 4
Spare
D
3
1
D
2
0
1
0
1
Surplus after dividing
0
3
2
1
Example of leap year
96, 00
These selections are for resetting 5-stage and the busy circuit after 1/2
15
frequency stage.
Resetting is activated by latching this code on to the address latch and setting WRITE=H
By latching this code to the address latch and setting READ to H, the standard
signals will be output at D
0
to D
3
Note:
Do not enter erroneous data for clock.
This may result in time keeping error.
Do not change STOP more than once while in BUSY mode.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D
3
A
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
2
A
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D
1
A
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
A
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Name of
register
S
1
S
10
MI
1
MI
10
H
1
H
10
W
D
1
D
10
MO
1
MO
10
Y
1
Y
10
—
—
D
3
S
8
mi
8
h
8
24/12
d
8
mo
8
y
8
y
80
1 hour
Leap year selection
D
2
S
4
S
40
mi
4
mi
40
h
4
PM/AM
W
4
d
4
mo
4
y
4
y
40
1 min.
D
1
S
2
S
20
mi
2
mi
20
h
2
h
20
W
2
d
2
d
20
mo
2
y
2
y
20
1 sec.
D
0
S
1
S
10
mi
1
mi
10
h
1
h
10
W
1
d
1
d
10
mo
1
mo
10
y
1
y
10
1024 Hz
Count
0 to 9
0 to 5
0 to 9
0 to 5
0 to 9
0 to 2
or
0 to 1
0 to 6
0 to 9
0 to 3
0 to 9
0 to 1
0 to 9
Note
1- sec. digit register
10 - sec. digit register
1 - min. digit register
10 - min. digit register
1 - hour digit register
10 - hour digit register
Week register
1 - day digit register
10 - day digit register
1- month digit register
10
-
month digit register
1
-
year digit register
10
-
year digit register
Reset register
Standard signal register
0==
“
L
”
level 1=
“
H
”
level
Item
CS setup time
Address setup time
Address write pulse width
Address hold time
Data setup time
Write pulse width
Data hold time
Read inhibit time
Read access time
Read delay time
CS hold time
1
t
RA
=1 μs+C x R x In [V
DD
/(V
DD
-V
H
)]
Symbol
t
CS
t
AS
t
AW
t
AM
t
DS
t
WW
t
CH
t
RI
t
RA
t
DD
t
CH
Condition
—
Min.
0
0.5
0.1
0
2
0
—
0
Typ.
—
Max.
—
1
1
—
Unit.
μs
(V
DD
=5 V±0.5 V)
C: Data line capacity
R: Pull-up resistance
V
H
:
“
H
”
input voltage connected to the data line
In: Natural logarithm
after dividing
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