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參數(shù)資料
| 型號： | RTC-4701JE |
| 廠商： | 愛普生（中國）有限公司 |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Serial RTC Module With Alarm and Timer Functions and Built-In Temperature Sensor(串行接口實時時鐘模塊（帶報警器和時鐘）) |
| 中文描述： | 串行實時時鐘模塊與報警和定時器功能和內(nèi)置的溫度傳感器（串行接口實時時鐘模塊（帶報警器和時鐘）） |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 99K |
| 代理商： | RTC-4701JE |
66
Real time clock module
V
TEMP
SOFF
Switching characteristics
BANK1
BANK0
Block diagram
Register table
Timing chart
Bus interface circuit
Fout controller
Divider
Temperature
Sensor
F
OUT
F
OE
TIRQ
AIRQ
DATA
CLK
CE
Clock and Calendar
Timer register
Alarm register
Control register
and
System Controller
Degital Trimming register
Interrupts controller
OSC
32.768 kHz
Control line
t
CH
t
RF
t
RF
t
WL
t
CLK
t
DS
t
DH
D0
D1
D6
D7
D0
D6
D7
D0
D1
D6
D7
D0
D6
D7
t
WZ
t
RZ
t
RD
(Read data)
t
WH
t
CS
t
CR
CE
CLK
DATA
Data Read
DATA
Data Write
50 %
10 %
90 %
90 %
(Write data)
From here the DATA pin turns into the output mode.
(Setup code, setup address)
(Setup code, setup address)
10 %
t
DO
0 : Always set this bit to
“
0
”
.
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Register symbol
Second
Minute
Hour
Day of Week
Day
Month
Year
Minutes Alarm
Hours Alarm
Day of week Alarm
Day Alarm
–
Timer setup
Timer Couner
Control 1
Control 2
bit 7
fos
fr
fr
fr
fr
fr
Year 80
AE
AE
AE
AE
–
TE
128
0
0
bit 6
S 40
Min 40
0
W 6
0
C
Year 40
A-Min 40
A-W 6
–
64
0
TEST
bit 5
S 20
Min 20
Hour 20
W 5
Day 20
0
Year 20
A-Min 20
A-Hr 20
A-W 5
A-Day 20
–
TD
1
32
0
STOP
bit 4
S 10
Min 10
Hour 10
W 4
Day 10
Month 10
Year 10
A-Min 10
A-Hr 10
A-W 4
A-Day 10
–
TD
0
16
TI/TP
RESET
bit 3
S 8
Min 8
Hour 8
W 3
Day 8
Month 8
Year 8
A-Min 8
A-Hr 8
A-W 3
A-Day 8
–
8
AF
HOLD
bit 2
S 4
Min4
Hour4
W 2
Day 4
Month 4
Year 4
A-Min 4
A-Hr 4
A-W 2
A-Day 4
–
4
TF
0
bit 1
S 2
Min 2
Hour 2
W 1
Day 2
Month 2
Year 2
A-Min 2
A-Hr 2
A-W 1
A-Day 2
–
2
AIE
0
bit 0
S 1
Min 1
Hour 1
W 0
Day 1
Month 1
Year 1
A-Min 1
A-Hr 1
A-W 0
A-Day 1
–
1
TIE
0
Address
B
C
D
E
F
Register symbol
additional counter 1
additional counter 2
–
–
control 3
bit 7
128
fr
–
–
FOES
bit 6
64
AC1
–
–
TEST
bit 5
32
AC0
–
–
–
bit 4
16
OVF
–
–
–
bit 3
8
2048
–
–
–
bit 2
4
1024
–
–
ACIE
bit 1
2
512
–
–
ACE
bit 0
1
256
–
–
SON
Item
CLK clock cycle
CLK H Pulse Width
CLK L Pulse Width
CE setup time
CE hold time
CE recovery time
Write data setup time
Write data hold time
Write data disable delay time
Output mode switching time
Read data delay time
Output disable time
Rise and fall time
FOUT duty ratio
(32.768kHz output)
Oscillation stop defection time
Symbol
t
CLK
t
WH
t
WL
t
CS
t
CH
t
CR
t
DS
t
DH
t
WZ
t
DO
t
RD
t
RZ
t
RF
Duty
t
OSC
Control
—
C
L
=50 pF
C
L
=50 pF
R
L
=10 k
—
Min.
600
300
400
75
0
—
40
10
Max.
—
300
200
100
60
—
Min.
350
175
300
50
0
—
40
10
Max.
—
120
100
50
60
—
Unit
ns
%
ms
(GND=0V,Ta=-40
C to +85
C)
V
DD
=3.0±10%
V
DD
=5.0±10%
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