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參數(shù)資料
| 型號： | RTC-4553 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | High-Frequency High-Stability Serial-Interface Real Time Clock Module(高頻率、高穩(wěn)定性、串行接口實時時鐘模塊) |
| 中文描述： | 高頻高穩(wěn)定性的串行接口實時時鐘模塊（高頻率，高穩(wěn)定性，串行接口實時時鐘模塊） |
| 文件頁數(shù)： | 2/2頁 |
| 文件大小： | 113K |
| 代理商： | RTC-4553 |
60
Real time clock module
Switching characteristics
Block diagram
Register table
Timing chart
32.768 kHz
TP
OUT
S
OUT
SCK
S
IN
CS
1
CS
0
WR
(Ta=-30
°
C to +70
°
C, V
DD
=5 V
±
10 %, GND=O V)
Note:
TEST bit should be
“
0
”
.
CS
0
SCK
S
IN
WR
S
OUT
S
OUT
CS
1
TP
OUT
SCK
CS
0
t
WCKL
t
SD
t
SWR
t
DSZ1
t
DSO
t
DPZ1
t
DPZ2
t
DSZ2
t
PS
t
HWR
t
HD
t
WCKH
t
HCS
1/f
CLK
10 %
90 %
90 %
10 %
90 %
10 %
90 %
90 %
10 %
90 %
90 %
10 %
10 %
10 %
90 %
10 %
10 %
t
SCS
SCK
OSC
Counter
Output
control
RAM
(120bit)
Input
control
Output control
Shift register
Control circuit
Control
register
1
Control
register
2
Control
register
3
Sec. Min. Hou.
Day
of
Week
Day Mon. Year
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MODE 0
Counter control register
Register
symbol
S
1
S
10
MI
1
MI
10
H
1
H
10
W
D
1
D
10
MO
1
MO
10
Y
1
Y
10
C
1
C
2
C
3
D
3
S
8
0
mi
8
0
h
8
PM/AM
0
d
8
0
mo
8
0
y
8
y
80
TPS
BUSY
SYSR
D
2
S
4
S
40
mi
4
mi
40
h
4
0
w
4
d
4
0
mo
4
0
y
4
y
40
30ADJ
PONC
TEST
D
1
S
2
S
20
mi
2
mi
20
h
2
h
20
w
2
d
2
d
20
mo
2
0
y
2
y
20
CNTR
—
MS
1
D
0
S
1
S
10
mi
1
mi
10
h
1
h
10
w
1
d
1
d
10
mo
1
mo
10
y
1
y
10
24/12
MS
0
Register name
1-second digit register
10-second digit register
1-minute digit register
10-minute digit register
1-hour digit register
10-hour digit register
Day of the week digit register
1-day digit register
10-day digit register
1-month digit register
10-month digit register
1-year digit register
10-year digit register
Control register 1
Control register 2
Control register 3
MODE 1
User RAM Domain 1
D
3
RA
3
RA
7
RA
11
RA
15
RA
19
RA
23
RA
27
RA
31
RA
35
RA
39
RA
43
RA
47
RA
51
RA
55
RA
59
D
2
RA
2
RA
6
RA
10
RA
14
RA
18
RA
22
RA
26
RA
30
RA
34
RA
38
RA
42
RA
46
RA
50
RA
54
RA
58
D
1
RA
1
RA
5
RA
9
RA
13
RA
17
RA
21
RA
25
RA
29
RA
33
RA
37
RA
41
RA
45
RA
49
RA
53
RA
57
D
0
RA
0
RA
4
RA
8
RA
12
RA
16
RA
20
RA
24
RA
28
RA
32
RA
36
RA
40
RA
44
RA
48
RA
52
RA
56
MODE 2
User RAM Domain 2
D
3
RA
63
RA
67
RA
71
RA
75
RA
79
RA
83
RA
87
RA
91
RA
95
RA
99
RA
103
RA
107
RA
111
RA
115
RA
119
D
2
RA
62
RA
66
RA
70
RA
74
RA
78
RA
82
RA
86
RA
90
RA
94
RA
98
RA
102
RA
106
RA
110
RA
114
RA
118
D
1
RA
61
RA
65
RA
69
RA
73
RA
77
RA
81
RA
85
RA
89
RA
93
RA
97
RA
101
RA
105
RA
109
RA
113
RA
117
D
0
RA
60
RA
64
RA
68
RA
72
RA
76
RA
80
RA
84
RA
88
RA
92
RA
96
RA
100
RA
104
RA
108
RA
112
RA
116
Same as MODE 0
Same as MODE 0
Item
___
___
input frequency
SCK
“
L
”
time
SCK
“
H
”
time
SCK
pause time
CS
0
setup time
CS
0
hold time
S
IN
data setup time
S
data Hold time
___
setup time
___
hold time
WR
WR
OUT
delay time
__
, and CS
1
enable to
S
OUT
output
__
disable to S
OUT
high Z
CS
0
CS
0
CS
1
enable to S
OUT
output
CS
1
enable to S
OUT
high Z
Symbol
f
CLK
t
WCKL
t
WCKH
t
PS
t
SCS
t
HCS
t
SD
t
HD
t
SWR
t
HWR
t
DSO
t
DSZ1
t
DSZ2
t
DPZ1
t
DPZ2
Condition
—
—
C
L
=100 pF
Min.
—
1.0
0
0.5
0.2
1.0
0.5
—
Typ.
—
—
150
—
Max.
500
—
—
500
100
Unit
kHz
μs
ns
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