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參數(shù)資料
| 型號： | RT9262CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HARNESS CLIP MOUNT RoHS Compliant: Yes |
| 中文描述： | 高效率，低電源電流，升壓型DC / DC變換器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 110K |
| 代理商： | RT9262CS |
RT9262/A
Preliminary
www.richtek.com
8
DS9262/A-04 August 2002
Application Note
Output Voltage Setting
Referring to application circuits Fig.1 to Fig.5, the
output voltage of the switching regulator (V
OUT1
) can
be set with Eq.1.
The LDO output voltage (V
OUT2
of RT9262) can be
set with Eq.2.
1
R
1
V
1
OUT
×
+
=
And trip point of the low battery detector is 0.86V at
LBI pin of RT9262A.
Feedback Loop Design
Referring to application circuits Fig.1 to Fig.5, The
selection of R1, R2, R3, and R4 based on the trade-
off between quiescent current consumption and
interference immunity is stated below:
Follow Eq.1 and Eq.2.
Higher R reduces the quiescent current (Path
current = 1.25V/R2, and 0.86V/R3), however
resistors beyond 5M
are not recommended.
Lower R gives better noise immunity, and is less
sensitive to interference, layout parasitics, FB/LFB
node leakage, and improper probing to FB/LFB
pins.
A proper value of feed forward capacitor parallel
with R1 (or R4) on Fig.1 to Fig.5 can improve the
noise immunity of the feedback loops, especially in
an improper layout. An empirical suggestion is
around 100pF ~ 1nF for feedback resistors of M
,
and 10nF ~ 0.1
μ
F for feedback resistors of tens to
hundreds K
.
For applications without standby or suspend modes,
lower values of R1 to R4 are preferred. For
applications concerning the current consumption in
standby or suspend modes, the higher values of R1
to R4 are needed. Such “high impedance feedback
loops” are sensitive to any interference, which require
careful layout and avoid any interference, e.g.
probing to FB/LFB pins.
PRECAUTION 1
: Improper probing to FB or LFB pin
will cause fluctuation at V
OUT1
and V
OUT2
. It may
damage RT9262/A and system chips because V
OUT1
may drastically rise to an over-rated level due to
unexpected interference or parasitics being added to
FB pin.
PRECAUTION 2
: Disconnecting R1 or short circuit
across R2 may also cause similar IC damage as
described in precaution 1.
PRECAUTION 3
: When large R values were used in
feedback loops, any leakage in FB/LFB node may
also cause V
OUT1
and V
OUT2
voltage fluctuation, and
IC damage. To be especially highlight here is when
the air moisture frozen and re-melt on the circuit
board may cause several
μ
A leakage between IC or
component pins. So, when large R values are used in
feedback loops, post coating, or some other
moisture-preventing processes are recommended.
Layout Guide
A full GND plane without gap break.
V
OUT1
to GND noise bypass – Short and wide
connection for C2 to Pin1 and Pin6.
V
IN
to GND noise bypass – Add a 100
μ
F
capacitor close to L1 inductor, when VIN is not an
idea voltage source.
Minimized FB/LFB node copper area and keep
far away from noise sources.
Minimized parasitic capacitance connecting to LX
and EXT nodes, which may cause additional
switching loss.
The following diagram is an example of 2-layer
board layout for application circuits Fig.1 to Fig.4.
V
25
.
)
2
R
Eq.1
V
86
.
×
)
3
R
4
R
1
V
2
OUT
+
=
Eq.2
Prober Parasitics
FB Pin
R1
R2
V
OUT1
_
Q
+
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