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參數(shù)資料
| 型號： | RT9237CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MULTI-PHASE DC/DC CONTROLLER FOR CPU CORE POWER SUPPLY |
| 中文描述： | 多相DC / DC控制器的CPU內(nèi)核供電 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 323K |
| 代理商： | RT9237CS |
Preliminary
RT9237
DS9237-00 January 2002
www.richtek-ic.com.tw
9
V
V
O
IN
The sensing circuit gets I
X
= by local feedback.
R
SP
= R
SN
to cancel the voltage drop caused by GM
amplifier input bias current. I
X
is sampled and held
just before low side MOSFET turns off (See Fig.2).
Therefore,
, ,
SP
R
, for operating frequency = 200kHz
Fig. 2 Inductor Current and PWM Signal
Droop Tuning
The S/H current signals from power channels are
injected to ADJ pin to create droop voltage.
2
R
V
The DAC output voltage decreases by V
ADJ
to form
the VCORE load droop(see Fig.3).
Fig. 3 Droop Tune Circuit
Protection and SS function
For OVP, the RT9237 detects the V
CORE
by V
SEN
pin. Eliminate the parasitic delay and noise influence
on the PCB path for fast and accurate detection. The
trip point of OVP is 120% of normal output level. The
PWM outputs are pulled low to turn on the low side
MOSFET and turn off the high side MOSFET of the
synchronous rectifier at OVP. The OVP latch can
only be reset by VDD or DVD restart power on reset
sequence. The PGOOD detection trip point of V
CORE
is
±
8% out of the normal level. The PGOOD open
drain output pulls low when V
OCRE
exceeds the
range.
Soft start circuit generates a ramp voltage by
charging external capacitor with 10uA current after IC
POR acts. The PWM pulse width and V
CORE
are
clamped by the rising ramp to reduce the in-rush
current and protect the power devices.
Over current protection trip point is set by the resistor
R
IMAX
connected to IMAX pin. OCP is triggered if one
channel S/H current signal I
X
> . Controller
forces PWM output latched at high impedance to turn
off both high and low side MOSFET in the power
stage and initial the hiccup mode protection. The SS
pin voltage is pulled low with a 10
μ
A current after it is
less than 90% VDD. The converter restarts after SS
pin voltage < 0.2V. Three times of OCP disable the
converter and only release the latch by POR acts
(see Fig.4).
Fig. 4
SP
R
2
L
SP
S
IN
L
2
O
IN
O
)
AVG
(
L
)
H
/
S
(
X
R
R
S
5
V
V
V
V
I
I
×
μ
×
=
∑
×
=
X
ADJ
ADJ
I
3
R
2
+
_
EA
∑
∑
I
X
FB
COMP
V
DAC
- V
ADJ
+
_
V
DAC
V
ADJ
ADJ
R
ADJ
2/3 I
X1
2/3 I
X2
2/3 I
X3
2/3 I
X4
0A
0V
2V
4V
T0T1
T2
T3T4
TIME
COUNT = 1
COUNT = 2
COUNT = 3
OVERLOAD
APPLIED
SS
V
CORE
I
L
Falling Slope = V
O
/L
I
L
I
L (S/H)
I
L (AVG)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Inductor Current
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