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參數(shù)資料
| 型號： | RT9204 |
| 英文描述： | Step-down DC/DC Converter |
| 中文描述： | 降壓直流/直流轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 315K |
| 代理商： | RT9204 |
RT9203/A
Preliminary
www.richtek.com
12
DS9203/A-04 May 2003
+
FBL
RT9203/A
R3
BOOT
DRV
VCC = 5V
R4
R4
<
1K
Max. 5V
V
OUT2
≤
2.5V
VCC
Suggest Low
V
T
MOSFET
+
FBL
VCC
RT9203/A
R3
BOOT
DRV
V
BOOT
= 12V
R4
R4
<
1K
6V
Max. 6V
V
OUT2
≤
3.3V
Suggest Low
V
T
MOSFET
Input / Output Capacitor
High frequency/long life decoupling capacitors should
be placed as close to the power pins of the load as
physically possible. Be careful not to add inductance
to the PCB trace, as it could eliminate the
performance from utilizing these low inductance
components. Consult with the manufacturer of the
load on specific decoupling requirements.
The output capacitors are necessary for filtering
output and stabilizing the close loop (see the PWM
loop stability). For powering advanced high-speed
processors, it is required to meet fast load transient
requirement. Also high ESR usually induces ripple
that may trigger UV or OV protections. So High
frequency capacitors with low ESR/ESL capacitors are
recommended here.
Linear Regulator Driver
The linear controller of RT9203/A was designed to
drive an external bipolar NPN transistor or a MOSFET.
For a MOSFET, normally DRV need to provide
minimum V
OUT2
+VT+gate-drive voltage to keep
V
OUT2
as the set voltage. When driving MOSFET
operating at a 5V power supply, the gate-drive will be
limited at 5V. At this situation, as shown in Fig.7, a
MOSFET with low VT threshold (VT = 1V) and set
Vout2 below 2.5V are suggested. In V
BOOT
= 12V
operation condition, as Fig.8 shown, VCC is regulated
higher than 6V, which providing higher gate-drive
capability for driving the MOSFET, V
OUT2
can be set
as V
OUT2
≤
3.3V.
Fig. 7
Fig. 8
PWM Loop Stability
The RT9203/A is a voltage mode buck controller
designed for 5V step-down applications. The gain of
error amplifier is fixed at 35dB for simplifying design.
The output amplitude of ramp oscillator is 1.6V, the
loop gain and loop pole/zero are calculated as follows:
DC loop gain G
A
= 35dB
×
×
LC filter pole P
O
=
Error Amp pole P
A
= 300kHz
ESR zero Z
O
=
The RT9203/A Bode plot is as shown in Fig.9. It is
stable in most of application conditions.
Loop Gain
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
Z
O
= 3.2kHz
P
O
= 2.9kHz
L=2
μ
H
C
OUT
= 1500
μ
F(33m
)
V
OUT
= 3.3V
40
30
20
10
1M
100k
10k
1k
100
Fig.9
75
.
5
VOUT
8
LC
2
π
1
C
ESR
2
π
1
×
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