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參數(shù)資料
| 型號： | RT9173DPSP |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator |
| 中文描述： | 成本效益，峰值3A條接收器/源總線終端穩(wěn)壓器 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 233K |
| 代理商： | RT9173DPSP |
RT9173D
5
www.richtek.com
DS9173D-05 September 2007
Note 1.
Stresses listed as the above
"Absolute Maximum Ratings"
may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2.
Devices are ESD sensitive. Handling precaution recommended.
Note 3.
The device is not guaranteed to function outside its operating conditions.
Note 4.
θ
JA
is measured in the natural convection at T
A
= 25
°
C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of
θ
JC
is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 5.
V
OS
offset is the voltage measurement defined as V
OUT
subtracted from V
REFEN
.
Note 6.
Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
Note 7.
Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (V
IL
< 0.2V). It is measured with V
IN
= V
CNTL
= 5V.
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