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參數(shù)資料
| 型號(hào)： | RT9173DGSP |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator |
| 中文描述： | 成本效益，峰值3A條接收器/源總線終端穩(wěn)壓器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 233K |
| 代理商： | RT9173DGSP |
RT9173D
3
www.richtek.com
DS9173D-05 September 2007
Functional Pin Description
VIN (Pin 1)
Input voltage which supplies current to the output pin.
Connect this pin to a well-decoupled supply voltage. To
prevent the input rail from dropping during large load
transient, a large, low ESR capacitor is recommended to
use. The capacitor should be placed as close as possible
to the VIN pin.
GND [Pin 2, Exposed pad (9)]
Common Ground (Exposed pad is connected to GND).
The GND pad area should be as large as possible and
using many vias to conduct the heat into the buried GND
plate of PCB layer.
REFEN (Pin 3)
Reference voltage input and active low shutdown control
pin. Two resistors dividing down the VIN voltage on the pin
to create the regulated output voltage. Pulling the pin to
ground turns off the device by an open-drain, such as
2N7002, signal N-MOSFET.
Function Block Diagram
GND
VCNTL
REFEN
Current Limit
Thermal Protection
VOUT
EA
+
-
VIN
VOUT (Pin 4)
Regulator output. VOUT is regulated to REFEN voltage
that is used to terminate the bus resistors. It is capable of
sinking and sourcing current while regulating the output
rail. To maintain adequate large signal transient response,
typical value of 1000
μ
F AL electrolytic capacitor with 10
μ
F
ceramic capacitors are recommended to reduce the effects
of current transients on VOUT.
VCNTL (Pin 6)
VCNTL supplies the internal control circuitry and provides
the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin
to 3.3V bias
supply to handle large output current with at least 10
μ
F
capacitor from this pin to GND.
NC (Pin 5, 7, 8)
No Internal Connect.
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