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參數資料
| 型號： | RT9173CPSP |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Cost-Effective, 2A Sink/Source Bus Termination Regulator |
| 中文描述： | 成本效益，甲匯/源總線終端穩(wěn)壓器 |
| 文件頁數： | 11/13頁 |
| 文件大小： | 235K |
| 代理商： | RT9173CPSP |
RT9173C
11
DS9173C-12 September 2007
www.richtek.com
Figure 5
R
DS(ON)
vs. Temperature
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50
-25
0
25
50
75
100
125
Temperature
R
D
(
)
(
°
C)
V
CNTL
= 5V
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9173C. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between RT9173C and
the preceding power converter.
Thermal Consideration
RT9173C regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed maximum operation
junction temperature 125
°
C. The power dissipation
definition in device is:
P
D
= (V
IN
- V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:
P
D(MAX)
= ( T
J(MAX)
-T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125
°
C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance. The
junction to ambient thermal resistance (
θ
JA
is layout
dependent) for SOP-8 package (Exposed Pad) is 75
°
C/W
on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at T
A
= 25
°
C can
be calculated by following formula:
P
D(MAX)
= (125
°
C - 25
°
C) / 75
°
C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 7, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Ambient
Molding Compound
Gold Line
Lead Frame
Die Pad
Case (Exposed Pad)
Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing
Figure 7. Thermal Resistance Equivalent Circuit
Junction
R
DIE
R
DIE-ATTACH
R
DIE-PAD
R
GOLD-LINE
R
LEAD FRAME
Case
(Exposed Pad)
R
PCB
R
PCB
Ambient
R
MOLDING-COMPOUND
path 1
path 2
path 3
The thermal resistance
θ
JA
of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the expose pad of SOP-8 package.
About PCB layout
,
the Figure 8 show the relation between
thermal resistance
θ
JA
and copper area on a standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
T
A
= 25
°
C.We have to consider the copper couldn't stretch
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相關代理商/技術參數 |
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|---|---|
| RT9173DGSP | 功能描述:IC REG BUS TERMINATION 3A 8SOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:2,000 系列:- 應用:控制器，DSP 輸入電壓:4.5 V ~ 25 V 輸出數:2 輸出電壓:最低可調至 1.2V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:30-TFSOP（0.173"，4.40mm 寬） 供應商設備封裝:30-TSSOP 包裝:帶卷 (TR) |
| RT9173GS | 功能描述:IC REG BUS TERMINATION 1.5A 8SOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:43 系列:- 應用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數:1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應商設備封裝:48-QFN（7x7） 包裝:管件 |
| RT9173PS | 制造商:RICHTEK 功能描述:REGULATOR |
| RT9174GS | 功能描述:IC REG CTRLR TRPL POS ADJ 8SOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性晶體管驅動器 系列:- 產品培訓模塊:More Information on LDOs 標準包裝:2,500 系列:- 類型:正，固定式 輸出數:2 輸出電壓:2.8V，3.3V 電流 - 電源:12mA 輸入電壓:5 V ~ 22 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| RT9174PS | 制造商:Richtek Technology Corporation 功能描述: |
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