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參數(shù)資料
| 型號： | RSC-412864LQFP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Speech Recognition Processor |
| 中文描述： | 語音識別處理器 |
| 文件頁數(shù)： | 25/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | RSC-412864LQFP |
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Data Sheet
RSC-4128
“irq” bits can be cleared by writing a “0” to the corresponding bit at register FE (the “irq” register). “irq” bits cannot
be set by writing to register FE. Writing a “1” to that register is a NO-OP.
The “irq” bits must be cleared within the interrupt handler by an explicit write to the “irq” register rather than by an
implicit interrupt acknowledge.
PLEASE NOTE:
Clear interrupts this way –
mov irq, #bitmask
; CORRECT
Not this way –
And irq, #bitmask
; INCORRECT
The “and” instruction is not atomic. The “and” instruction is a read-modify-write action. If an interrupt occurs during
an “and irq” operation the interrupt will be cleared before it is seen, possibly disabling the interrupt until the system
is reset. Because one cannot directly set or clear bits in the “irq” register, use “mov irq” as a safe, effective and
atomic way to clear bits in the “irq” register. Use it the way you would use an “and” instruction to operate on other
registers.
NOTE: Bit2 and Bit5 of the “irq” register should always be written as “1” when clearing other “irq” bits, to avoid
conflicts with the Technology code use of these bits.
In Idle mode, Timer2 continues to operate even when the rest of the RSC-4128 is powered-down. An overflow
from Timer2 will set the corresponding “irq” flag even when there is no clock input to the processor. Note that the
Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup interrupt request to
occur. This may also lead to normal interrupt processing once the processor is active, if the Timer 2 “imr” bit is set
(register FD.Bit1). This interrupt response is unique from, and may be in addition to, the T2 Wakeup.
25
P/N 80-0206-J
2004 Sensory Inc.
Analog input
The analog front end (AFE) for the RSC-4128 consists of a preamplifier with gain control, a 16-bit analog-to-digital
converter, digital decimator and channel filters, and associated references. A single analog input can be processed
through the AFE.
All of this circuitry can be powered down to conserve battery life by programming register EF.Bit0
to “0”. Setting this bit to “1” powers up the circuitry, requiring a settling time of approximately 10milliseconds.
The analog front end (AFE) performs analog to digital conversions on a low-level signals, which may be derived
from an electret microphone. The microphone signal is amplified by a preamp that provides four levels of gain,
which are selected by programming register D5.Bits[4:3]. Full-scale output for the four settings corresponds to
input signals of 100, 50, 25, and 12.5 millivolts Vpeak-peak, as shown in the table below.
Gain
Input Referred
Noise
“sysCtl”
Bits[4:3]
00
5.2*
01
4.9*
10
4.6*
11
4.4
Input signals higher than specified will produce a saturated full scale output with no wrap around.
A line level audio
input must be attenuated to the range shown above for use with the AFE.
Max Input Signal
μ
Vrms
mVp-p
mVrms
100
50
25
12.5
35.4
17.7
8.8
4.4
相關(guān)PDF資料 |
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| RSC4128 | Speech Recognition Processor |
| RT1A3906 | |
| RT1N44BC | TRANSISTOR |
| RT1N44BM | TRANSISTOR |
| RT1N44BS | TRANSISTOR |
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