
2004 Fairchild Semiconductor Corporation
RMWB12001 Rev. C
R
Electrical Characteristics
(At 25°C), 50
system, Vd = +4V, Quiescent Current Idq = 96mA
Note:
1:
Typical range of gate voltage is -0.7 to 0.1V to set typical Idq of 96mA.
Parameter
Min
8.5
Typ
Max
12
Units
GHz
V
dB
dB
dBm
mA
%
dB
dB
V
Frequency Range
Gate Supply Voltage
Gain Small Signal (Pin = -15dBm)
Gain Variation vs. Frequency
Power Output Saturated: (Pin = -1dBm)
Drain Current Saturated (Pin = -1dBm)
Power Added Efficiency (PAE): at Psat
Input Return Loss (Pin = -15dBm)
Output Return Loss (Pin = -15dBm)
DC Detector Voltage at Pout = 20dBm
1
(Vg)
-0.2
25
3.0
21
120
26
12
10
0.5
23
18
23
220
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
Chip carrier material should be selected to have GaAs
compatible thermal coefficient of expansion and high
thermal conductivity such as copper molybdenum or copper
tungsten. The chip carrier should be machined, finished flat,
plated with gold over nickel and should be capable of
withstanding 325°C for 15 minutes.
Die attachment should utilize Gold/Tin (80/20) eutectic alloy
solder and should avoid hydrogen environment for PHEMT
devices. Note that the backside of the chip is gold plated
and is used as RF and DC ground.
These GaAs devices should be handled with care and
stored in dry nitrogen environment to prevent contamination
of bonding surfaces. These are ESD sensitive devices and
should be handled with appropriate precaution including the
use of wrist grounding straps. All die attach and wire/ribbon
bond equipment must be well grounded to prevent static
discharges through the device.
Recommended wire bonding uses 3 mils wide and 0.5 mil
thick gold ribbon with lengths as short as practical allowing
for appropriate stress relief. The RF input and output bonds
should be typically 0.012" long corresponding to a typical 2
mil gap between the chip and the substrate material.
Figure 1. Functional Block Diagram
1
Note:
1:
Detector delivers >0.1V DC into 3k
bond pad.
load resistor for > +20dBm output power. If output power level detection is not desired, do not make connection to detector
RF IN
Drain Supply
Vd1
Drain Supply
Vd2 and Vd3
Output Power
Detector Voltage Vdet
RF OUT
Gate Supply Vg
Ground (Back of Chip)
MMIC Chip