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參數資料
| 型號： | RMLA3565C-TB |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Wideband Low Noise MMIC Amplifier |
| 中文描述： | 寬帶單片低噪聲放大器 |
| 文件頁數： | 2/5頁 |
| 文件大?。?/td> | 257K |
| 代理商： | RMLA3565C-TB |
2004 Fairchild Semiconductor Corporation
RMLA3565C Rev. C
R
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount
package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for 3.5 to 6.5 GHz applications.
Figure 1 shows the functional block diagram of the packaged product.
Test Fixture
Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing
external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the
schematic diagram. Typical performance of the test fixture is shown in the performance data section. The following should
be noted:
(1) Package pin designations are shown in Figure 2.
(2) Vd is the drain voltage (positive) applied at the pins of the package.
(3) Vdd is the positive supply voltage at the evaluation board terminal.
Figure 1. Functional Block Diagram
Figure 2. Package Outline Dimensions
MMIC CHIP
Vd
Pin# 12
GROUND
Pin# 5
GROUND
Pin# 1, 3, 4, 6, 9, 10, 11, 13
RF IN
Pin# 8
GROUND
Pin# 7
RF OUT
Pin# 2
6
5
0.200 SQ.
0.011
0.030
0.020
0.015
4
4
5
Bottom View
Top View
Plastic Lid
Side Section
6
12 11 10
7
8
9
3
2
1
10
3
2
1
7
8
9
11 12
0.041
0.075 MAX
0.010
Dimensions in inches
0.282
0.246
0.230
Pin
10
11
12
13
Description
1
2
3
4
5
6
7
8
9
GND
RF Out
GND
GND
GND
GND
GND
RF In
GND
GND
GND
Vd
GND
(Package Base)
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