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參數(shù)資料
| 型號： | RM5271-200S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 387K |
| 代理商： | RM5271-200S |
6
RM5271 Microprocessor, Document Rev. 1.3
Quantum Effect Devices
www.qedinc.com
Figure 4 Kernel Mode Virtual Addressing (32-bit)
When the RM5271 is configured as a 64-bit microproces-
sor, the virtual address space layout is an upward compati-
ble extension of the 32-bit virtual address space layout.
Joint TLB
For fast virtual-to-physical address translation, the RM5271
uses a large, fully associative TLB that maps 96 virtual
pages to their corresponding physical addresses. As indi-
cated by its name, the joint TLB, or JTLB, is used for both
instruction and data translations. The JTLB is organized as
48 pairs of even-odd entries, and maps a virtual address
and address space identifier into the large, 64GB physical
address space.
Two mechanisms are provided to assist in controlling the
amount of mapped space and the replacement characteris-
tics of various memory regions. First, the page size can be
configured, on a per-entry basis, to use page sizes in the
range of 4KB to 16MB (in multiples of 4). The CP0 Page-
Mask register is loaded with the desired page size of a
mapping, and that size is stored into the TLB along with the
virtual address when a new entry is written. Thus, operat-
ing systems can create special purpose maps. For exam-
ple, a entire frame buffer can be memory mapped using
only one TLB entry.
The second mechanism controls the replacement algorithm
when a TLB miss occurs. The RM5271 provides a random
replacement algorithm to select the TLB entry to be written
with a new mapping. However, the processor also provides
a mechanism whereby a system specific number of map-
pings can be locked into the TLB, thereby avoiding random
replacement. This mechanism allows the operating system
to guarantee that certain pages are always mapped for per-
formance reasons and for deadlock avoidance. This mech-
anism also facilitates the design of real-time systems by
allowing deterministic access to critical software.
The JTLB also contains information that controls the cache
coherency protocol for each page. Specifically, each page
has attribute bits to determine whether the coherency algo-
rithm is one of the following:
uncached
non-coherent write-back]
non-coherent write-through with write-allocate
non-coherent write-through without
write-allocate
sharable
exclusive
update
Note that both of the write-through protocols bypass the
secondary cache since the secondary does not support
writes of less than a complete cache line. The non-coher-
ent protocols are used for both code and data on the
RM5271 with data using write-back or write-through
depending on the application.
The coherency attributes generate coherent transaction
types on the system interface. However, cache coherency
is not supported in the RM5271 and therefore the coher-
ency attributes should never be used.
Instruction TLB
The RM5271 implements a 2-entry instruction TLB (ITLB)
to minimize contention for the JTLB, eliminate the timing
critical path of translating through a large associative array,
and save power. Each ITLB entry maps a 4KB page. The
ITLB improves performance by allowing instruction address
translation to occur in parallel with data address translation.
When a miss occurs on an instruction address translation
by the ITLB, the least-recently used ITLB entry is filled from
the JTLB. The operation of the ITLB is completely transpar-
ent to the user.
Data TLB
The RM5271 implements a 4-entry data TLB (DTLB). Each
DTLB entry maps a 4KB page. The DTLB improves perfor-
mance by allowing data address translation to occur in par-
allel with instruction address translation. When a miss
occurs on a data address translation by the DTLB, the
DTLB is filled from the JTLB. The DTLB refill is pseudo-
LRU: the least recently used entry of the least recently
0xFFFFFFFF
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
0xE0000000
0xDFFFFFFF
Supervisor virtual address space
(ksseg)
Mapped, 0.5GB
0xC0000000
0xBFFFFFFF
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0xA0000000
0x9FFFFFFF
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x80000000
0x7FFFFFFF
User virtual address space
(kuseg)
Mapped, 2.0GB
0x00000000
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