參數(shù)資料
型號: RM3183D
元件分類: 接收器
英文描述: Line Receiver
中文描述: 線路接收器
文件頁數(shù): 5/45頁
文件大?。?/td> 287K
代理商: RM3183D
RM3182
PRODUCT SPECIFICATION
4
Principles of Operation
Each device consists of one differential driver and associated
gating circuitry. The gating circuitry consists of clock and
sync signal inputs which are ANDed with the two data
inputs. See the block diagram and truth table. Three power
supplies are required to operate the RM3182 in a typical
ARINC 429 bus application: +15V, -15V, and +5V. The +5V
supply, in addition to powering the internal bus current
regulator, provides a reference voltage that determines the
output voltage swing. The differential output swing will
equal 2 V
REF
.
If a value of V
REF
then a separate +5V supply is required for pin V1.
other than +5V is used,
Figure 1 depicts connections for the ARINC 429 application.
The driver output impedance is nominally 75
Data(A) input at a logic high and Data (B) input at a logic
W
. With the
low, A
V
REF
input states will cause A
to +V
REF
. With both data input signals at a logic low state,
the outputs will both swing to 0V (output in null state).
OUT
(constituting a logic high state). Reversing the data
OUT
to swing to -V
will swing to +V
REF
and B
OUT
will swing to
REF
and B
OUT
The slew rate of the outputs, and consequently rise and fall
times, can be adjusted through the selection of two external
capacitor values. Typical values are C
high-speed operation (100 Kbits/sec) and C
for low-speed operation (12.5 to 14 Kbits/sec).
A
= C
B
A
= 75 pF for
= C
B
= 500 pF
The device can be powered down by applying a logic high
signal to the Power Enable pin. If the power down feature is
not used, then the Power Enable pin should be tied directly
to ground.
Figure 1. ARINC 429 Bus Application
Data (A)
Data (B)
V
REF
V1
Sync
Clock
A
C
C
Gnd
Power
Enable
-V
S
B
Inputs
To Bus
4
13
+5V
+15V
-15V
RM3182
1
16
3
14
9
5
12
8
2
7
11
6
65-3182-04
OUT
OUT
A
B
+V
S
Note: Pin numbers are for
the 16-lead DIP.
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