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Preliminary
11-121
RF2968
Rev A13 010912
11
T
Pin
1
2
3
Function
VCC1
VCC2
TX OUT
Description
Supply voltage for the VCO doubler and LO amplifier circuits.
Interface Schematic
Supply voltage for the RX mixers, TX PA, and LNA bias circuits.
Transmitter output. TX OUT output impedance is 50
(nominal) when
the transmitter is enabled. TX OUT is a high impedance when the
transmitter is disabled. Because this pin is DC-biased, an external cou-
pling capacitor is required.
4
RX IN
Receiver input. RX IN input impedance is a low impedance when the
receiver is enabled. RX IN is a high impedance when the receiver is
disabled. An internal series inductor is used to tune the input imped-
ance.
5
VCC3
Supply voltage for the RX input stage (LNA).
6
VCC4
Supply voltage for the TX mixers and bias circuits of the LO amplifier,
LNA, and RX mixers.
Low frequency clock output for low power mode. In sleep mode, this pin
may provide either a 3.2kHz or 32kHz clock having a 50% duty cycle to
the baseband. In other modes, the output is disabled.
Supply voltage for the RX IF VGA circuit.
7
LPO
8
9
DVDDH
IREF
Connects an external precision resistor (1% tolerance) for generation
of a constant current reference.
Supply voltage for the analog IF circuits.
10
11
VCC5
D1
This is the output of the charge pump for clock recovery circuit. A RC
network from this pin to ground is used to establish the PLL bandwidth.
In transmit mode, this pin is used as a strobe to enable the PA stage. In
receive mode, the baseband has the option to use this pin to signal the
detection of the sync word. The baseband drives this pin high at the
end of the sync word, at which time a second DC estimation is per-
formed by sampling the trailer bits. If baseband control is not desired to
signal the second DC estimation, then an internal timer is used to mark
the end of the sync word. The BBC bit is used to select the baseband
control option; the default setting uses the internal timer.
Input data to transmitter/output data from receiver. The input data is
unfiltered data at 1MHz data rate. The pin is bidirectional, switching
between data in and data out modes during Transmit and Receive
modes respectively.
Recovered clock output.
See pin 26.
12
BPKTCTL
See pin 23.
13
BDATA1
14
15
16
RECCLK
RECDATA
BXTLEN
See pin 17.
Recovered data output.
See pin 17.
This pin is part of the chip power control circuit. It is used to enable/dis-
able “sleep” mode of chip.
TX OUT
10
V
CC
RX IN
V
CC3
VCC3
RXDATA
TX DATA
BDATA1
BXTLEN
V
CC