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參數(shù)資料
| 型號(hào)： | RF2679 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | RF2679 |
Preliminary
7-41
RF2679
Rev A0 000825
7
Q
D
Pin
1
Function
GC
Description
Analog Gain Control for AGC Amplifiers. The valid control range is from
0.3 to 2.4V
DC
. These voltages are valid for ONLY a 68k
source
impedance. The gain range for the AGC is 60dB.
Interface Schematic
2
DEC
AGC decoupling pin. An external bypass capacitor of 10nF capacitor is
required. The trace length between the pin and the bypass capacitor
should be minimized. The ground side of the bypass capacitor should
connect immediately to ground plane.
W-CDMA Balanced Input pin. This pin is internally DC biased and
should be DC blocked if connected to a device with a DC level present.
For single-ended input operation, one pin is used as an input and the
other W-CDMA input is AC coupled to ground. The balanced input
impedance is 2.4k
, while the single-ended input impedance is 1.2k
.
3
WCDMA IN+
4
5
WCDMA IN-
VCC1
Same as pin 4, except complimentary input.
See pin 3.
Supply voltage for the AGC input stage, band gap and gain control bias
circuitry. This pin may be connected in parallel with pins 6 and 7. It
should be bypassed by a 22nF capacitor. The trace length between the
pin and the bypass capacitor should be minimized. The ground side of
the bypass capacitor should connect immediately to ground plane. The
part is designed to work from a 2.7V to 3.3V supply.
Supply voltage for the bandgap, gain control bias circuitry, and AGC
stages 2 and 3. This pin may be connected in parallel with pins 5 and 7.
It should be bypassed by a 22nF capacitor. The trace length between
the pin and the bypass capacitor should be minimized. The ground side
of the bypass capacitor should connect immediately to ground plane.
The part is designed to work from a 2.7V to 3.3V supply.
Supply voltage for the LO divider and limiting amp. This pin may be
connected in parallel with pins 5 and 6. It should be bypassed by a
22nF capacitor. The trace length between the pin and the bypass
capacitor should be minimized. The ground side of the bypass capaci-
tor should connect immediately to ground plane. The part is designed
to work from a 2.7V to 3.3V supply.
Same as pin 12, except complementary input.
6
VCC2
7
VCC3
8
9
LO+
LO-
See pin 9.
LO Balanced Input pin. This pin is internally DC biased and should be
DC blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other LO input is
AC coupled to ground. The frequency of the signal applied to these
pins is internally divided by a factor of 4, hence the carrier frequency for
the modulator becomes one fourth of the applied frequency. The single-
ended input impedance is 400
(balanced is 800
). The LO input may
be driven single-ended but balanced provides optimum gain and phase
balance.
10
GND1
Ground connection. Keep traces physically short and connect immedi-
ately to ground plane for best performance.
Supply voltage for the baseband stage. This pin should be bypassed by
a 100nF capacitor.
11
VCC4
21 k
BIAS
40 k
GC
1200
1200
CDMA IN+
BIAS
BIAS
CDMA IN-
400
400
LO-
BIAS
BIAS
LO+
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