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參數(shù)資料
| 型號： | REJ03F0023_M61140FP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | TUNER SINGLE CHIP |
| 中文描述： | 調諧器單芯片 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 571K |
| 代理商： | REJ03F0023_M61140FP |
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M61140FP
Rev.1.2, Apr.16.2004, page 12 of 28
(1) WRITE mode
The information of 5 bytes required for circuit operational chip address, control data and band SW data of 2 bytes
and divider data of 2 bytes. after the chip address input, 2 or 4 bytes can be received. Function bit is contained in the
first and the third data byte to distinguish between divider and 'control data/band SW data', with "0" going ahead of
divider data, and "1" going ahead of 'control data/band SWdata'.
The timing of Writing data for bus protocol Mode is shown in the figure below. Divider data uses 15 bits and is read
in at the rise of the eighth clock bit of the second byte divider data (DB2). Control data (CB1) and band SW-data
(BB) are each read in at the rise of their eighth clock bit.
Timing Chart
Read into latch
Read into latch
Read into latch
address
DB1
DB2
CB1
CB2
SDA
SCL
Write mode data format
Byte
Address Byte (CA)
Divider Byte1 (DB1)
Divider Byte2 (DB2)
Control Byte (CB1)
Band Byte (CB2)
Programmable Address Bit
MSB
1
0
N7
1
X
1
N14
N6
CP
X
0
N13
N5
T2
X
0
N12
N4
T1
X
0
N11
N3
T0
PUHF
MA1
N10
N2
Rsa
PFMST PVHFH PVHFL
MA0
N9
N1
Rsb
LSB
R/W=0
N8
N0
OS
A
A
A
A
A
Address input voltage applied to ADS [V]
0 to 0.1xVcc
Open or 0.2 to 0.3xVcc
0.4xVcc to 0.6xVcc
0.9xVcc to Vcc
N14 to N0 : Set up for division ratio of the programmable divider
MA1
0
0
1
1
MA0
0
1
0
1
Frequency of VCO fvco: fvco=fref x N
Division ratio N: N=N14(2^14 )+N13(2^13 )+ --- +N0(2^0)
Range of division ratio N: N=1,024 to 32,767
fref: Reference frequency of phase comparator
CP: Set up the charge pump current
CP
0
1
Note:
*
Current of charge pump is typ current
In the case of setting current 270
μ
A,when PLL is locked, charge pump current is automatically switched to CP=O
(70
μ
A).
Charge pump current
*
70
μ
A
300
μ
A
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