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參數(shù)資料
| 型號： | RED |
| 廠商： | LSI Corporation |
| 英文描述： | AC LINE FREQUENCY DIVIDERS |
| 中文描述： | 交流線路分頻器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 47K |
| 代理商： | RED |
AC LINE FREQUENCY DIVIDERS
RED SERIES
RED 5/6 Divide by 5 or 6
RED 50/60 Divide by 50 or 60
RED 100/120 Divide by 100 or 120
RED 300/360 Divide by 300 or 360
RED 500/600 Divide by 500 or 600
RED 3000/3600 Divide by 3000 or 3600
FEATURES:
Clock input pulse shaper accepts 50Hz/60Hz
sine wave directly
Fully static counter operation
+4.5V to +15V operation (V
DD
- V
SS
)
Low power dissipation
High noise immunity
Reset
Input Enable
50Hz/60Hz division select input
Output low power TTL compatible at +4.5V operation
Square Wave Output (except for ÷ 5)
RED x/y (DIP); RED x/y-S (SOIC) See Figure 1
APPLICATION:
Time base generator from either 50Hz or 60Hz line
frequency to produce:
10 pulses per second (RED 5/6)
1 pulse per second (RED 50/60)
1 pulse per 2 seconds (RED 100/120)
1 pulse per .1 minute (RED 300/360)
1 pulse per 10 seconds (RED 500/600)
1 pulse per minute (RED 3000/3600)
DESCRIPTION OF OPERATION
:
The counter advances by one on each negative transition of the
input clock pulse as long as the Enable signal is High and the
Reset signal is Low. When the Enable signal is Low the input
clock pulses will be inhibited and the counter will be held at the
state it was in prior to bringing the Enable Low. A High Reset
signal clears the counter to zero count.
Depending on the device used, a Low on the Division Select in-
put will cause a Divide by 6, 60, 120, 360, 600 or 3600. A High
on the Division Select will cause a Divide by 5, 50, 100, 300, 500
or 3000.
All outputs are 50% duty cycle except RED 5, where output is
low for two clocks and high for three clocks.
CLOCK INPUT
If input signals are less than the Vss or greater than V
DD
, a
series input resistor should be used to limit the maximum input
current to 2 mA.
MARKING AS FOLLOWS:
PART
MARKING
RED 5/6
RED 50/60
RED 100/120
RED 300/360
RED 500/600
RED 3000/3600
RED 6
RED 60
RED 120
RED 360
RED 600
RED 3600
V
DD
(V+)
L
1
2
3
4
8
7
6
5
OUTPUT
RESET
V
SS
(-V)
NC
DIVISION SELECT
ENABLE
CLOCK INPUT
PIN ASSIGNMENT - TOP VIEW
FIGURE 1
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
RED-062600-1
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
RED SERIES
UL
A3800
July 2000
MAXIMUM RATINGS:
PARAMETER SYMBOL VALUE UNIT
Storage Temperature
T
STG
Operating Temperature
T
A
DC Supply Voltage
(V
DD
-Vss)
Voltage at any input
V
IN
-65 to +150
-40 to +85
+18
Vss -.3 to V
DD
+.3 V
C
C
V
ENABLE SIGNAL TIMING
If the Enable signal switches Low during a positive clock phase and
then switches High during a negative clock phase, a false count will
be registered. To prevent this from happening, the Enable signal
should not switch Low during a positive clock phase unless the
switch to High also occurs during a positive clock phase. The
Enable signal should normally be switched during a negative clock
phase.
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