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參數(shù)資料
| 型號： | RDC-19229S-172S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQCC44 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 276K |
| 代理商： | RDC-19229S-172S |
12
Data Device Corporation
www.ddc-web.com
RDC-19220/2S
E-11/02-300
DC INPUTS
As noted in TABLE 1 the RDC-19220/2S will accept DC inputs. It
is necessary to set the REF input to DC by tying +REF to +5 V
and -REF to GND or -5 \/. (With DC inputs, the BIT output is not
valid.)
VELOCITY TRIMMING
RDC-19220/2S specifications for velocity scaling, reversal error,
and offset are contained in TABLE 1. Velocity scaling and offset
are externally trimmable for applications requiring tighter specifi-
cations than those available from the standard unit. FIGURE 11
shows the setup for trimming these parameters with external
potentiometers. It should also be noted that when the resolution
is changed, VEL Scaling is also changed. Since the VEL output
is from an integrator with capacitor feedback, the VEL voltage
cannot change instantaneously. Therefore, when changing reso-
lution while moving, there will be a transient with a magnitude
proportional to the velocity and a duration determined by the
converter bandwidth.
8
10
-VCO
VEL
+5 V
-5 V
100 k
(OFFSET)
100 RV
0.8 RV
0.4 R (SCALING)
V
RDC-19220/2S
FIGURE 11. VELOCITY TRIMMING
TABLE 6. 12-BIT LVDT OUTPUT CODE
FOR FIGURE 12B
LVDT OUTPUT
MSB
LSB
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01
xxxx
00
1111
00
1100
0000
00
1000
0000
0001
00
1000
0000
00
0111
1111
00
0100
0000
00
0000
11
xxxx
COS
ωt reference input. The phase angle of the synthesized ref-
erence is determined by the signal input. The reference input is
used to choose between the +180° and -180° phases. The syn-
thesized reference will always be exactly in phase with the signal
input, and quadrature errors will therefore be reduced. The syn-
thesized reference circuit also eliminates the 180° false error null
hang up.
Due to the inductive nature of resolvers, the output signals typi-
cally lead the reference by 6°, and a 6° phase shift will cause
problems for a 2.3 arc minute accuracy converter. A synthesized
reference will always be exactly in phase with the signal input.
LVDT (LINEAR VARIABLE DIFFERENTIAL
TRANSFORMER) MODE
As shown in TABLE 1 the RDC-19220/2S unit can be made to
operate as a LVDT-to-digital converter by connecting Resolution
Control inputs A and B to “0,” “1,” or the -5 volt supply. In this
mode the RDC-19220/2S functions as a ratiometric tracking lin-
ear converter. When linear AC inputs are applied from an LVDT
the converter operates over one quarter of its range. This results
in two less bits of resolution for LVDT mode than are provided in
resolver mode.
The LVDT output signals will need to be scaled to be compatible
with the converter input. FIGURE 12B is a schematic of an input
scaling circuit applicable to 3-wire LVDTs. The value of the scal-
ing constant “a” is selected to provide an input of 2 Vrms at full
stroke of the LVDT. The value of scaling constant “b” is selected
to provide an input of 1 Vrms at null of the LVDT. Suggested com-
ponents for implementing the input scaling circuit are a quad op-
amp, such as a 4741 type, and precision thin-film resistors of
0.1% tolerance. FIGURE 12A illustrates a 2-wire LVDT configu-
ration.
Data output of the RDC-19220/2S is Binary Coded in LVDT
mode. The most negative stroke of the LVDT is represented by
ALL ZEROS and the most positive stroke of the LVDT is repre-
sented by ALL ONES. The most significant 2 bits (2 MSBs) may
be used as overrange indicators. Positive overrange is indicated
by code “01” and negative overrange is indicated by code “11”
(see TABLE 6).
SYNTHESIZED REFERENCE
The synthesized reference section of the RDC-19220/2S elimi-
nates errors caused by quadrature voltage which is due to a
phase shift between the reference and the signal lines.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. Due to the inductive nature of synchros and
resolvers, their signals lead the reference signal (RH and RL) by
about 6°.
When an uncompensated reference signal is used to demodu-
late the control transformer’s output, quadrature voltages are not
completely eliminated. As shown in FIGURE 1, the converter
synthesizes its own COS(
ωt + α) reference signal from the SIN θ
COS(
ωt + α), COS θ COS(ωt + θ ) signal inputs and from the
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