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參數(shù)資料
| 型號： | RDC-19229-422L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQCC44 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 256K |
| 代理商： | RDC-19229-422L |
15
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
;;
;;;
DATA
VALID
300 ns max
INHIBIT
;
100 ns MAX
ENABLE
150 ns MAX
DATA
VALID
HIGH Z
;
1/40 FS
(375 nsec nominal)
CB
50 ns
DATA
VALID
DATA
VALID
FIGURE 13. INHIBIT TIMING
FIGURE 14. ENABLE TIMING
FIGURE 15. CONVERTER BUSY TIMING
constant “a” is selected to provide an input of 2 Vrms at full stroke
of the LVDT. The value of scaling constant “b” is selected to pro-
vide an input of 1 Vrms at null of the LVDT. Suggested compo-
nents for implementing the input scaling circuit are a quad op-
amp, such as a 4741 type, and precision film resistors of 0.1%
tolerance. FIGURE 12A illustrates a 2-wire LVDT configuration.
Data output of the RDC-19220 Series is Binary Coded in LVDT
mode. The most negative stroke of the LVDT is represented by
all zeros and the most positive stroke of the LVDT is represent-
ed by all ones. The most significant 2 bits (2 MSBs) may be used
as overrange indicators. Positive overrange is indicated by code
“01” and negative overrange is indicated by code “11” (see
TABLE 7).
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 13,
angular output data is valid 300 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 14, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 15,
output data is valid 50 ns maximum after the middle of the CB
pulse. CB pulse width is 1/40 Fs, which is nominally 375 ns.
BUILT-IN-TEST (BIT)
The Built-ln-Test output (BIT) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 1 to a logic 0.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null. BIT will also be set low for a detected
total Loss-of-Signal (LOS). The BIT signal may pulse during cer-
tain error conditions (i.e., converter spin around or signal ampli-
tude on threshold of LOS).
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak.
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