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參數(shù)資料
| 型號(hào)： | RDC-19222-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 1233K |
| 代理商： | RDC-19222-202 |
11
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
V-12/08-0
R i
S1
S3
+S
-S
SIN
Rf
R i
Rf
R i
S4
S2
+C
-C
Rf
R i
Rf
COS
A GND
CONVERTER
8 10
-
+
-
+
RESOLVER
INPUT
R i
S1
S3
+S
-S
SIN
Rf
R i
Rf
R i
S4
S2
+C
-C
Rf
R i
Rf
COS
A GND
CONVERTER
8 10
12
15
13
2
3
1
6
16
7
4
5
-
+
-
+
RESOLVER
INPUT
Notes:
1) S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to gND at the converter.
2) For 2V direct input use 10k matched resistors for Ri & Rf.
Examples of Component Calculations:
Component Formula
Ri x 2 Vrms = Resolver L-L rms voltage
Rf
Rf ≥ 6 k
1) 2V in, need gain of 1, use 10k for Rf and Ri
gain = Rf/Ri
2) 4V in, need gain of 0.5, Rf = 10k, Ri = 20k
To calculate Ri:
Select 10k for Rf
Ri = Rf x 0.5 x (input L-L volt)
Ri = 10k x 0.5 x (input L-L volt)
FIGURE 8A. dIFFERENTIAL REsOLVER INPUT
FIGURE 8B. dIFFERENTIAL REsOLVER INPUT, UsING ddc-49530, ddc-57470 (11.8 V),
ddc-73089 (2V), OR ddc-49590 (90 V)
1) S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to gND at the converter.
2) For DDC-49530 or DDC-57470: Ri = 70.8 k
, 11.8 V input, synchro or resolver. For DDC-49590: Ri = 270 k, 90 V input, synchro or resolver.
3) Maximum additional error is 1 LSB using recommended thin film package.
4) Note on dc Offset Gains: Input options affect DC offset gains and therefore affect carrier frequency ripple and jitter. Offsets gains associated with differ-
ential mode, (offset gain for differential configuration = 1 + RF/RI) and direct mode (offset gain for direct configuration = 1), show differential will always be
higher. Higher DC offsets cause higher carrier frequency ripple due to demodulation process. This carrier frequency ripple because it is riding on the top of
the DC error signal causes jitter. A higher carrier frequency vs bandwidth ratio will help decrease ripple and jitter associated with offsets. Summary: R/D’s with
differential inputs are more susceptible to offset problems than R/D’s in single ended mode. RD’s in higher resolutions, such as 16 bit, will further compound
offset issues due to higher internal voltage gains. Although the differential configuration has a higher DC offset gain, the differential configuration’s common
mode noise rejection makes it the preferred input option. The tradeoffs should be considered on a design to design basis. Also refer to FAQ-gIQ-021.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RDC-19222-202T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LVDT/Resolver-to-Digital Converter |
| RDC-19222-203 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LVDT/Resolver-to-Digital Converter |
| RDC-19222-203T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LVDT/Resolver-to-Digital Converter |
| RDC-19222-301 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LVDT/Resolver-to-Digital Converter |
| RDC19222-301 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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