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參數(shù)資料
| 型號(hào)： | RDC-19220-422Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | 2 X 0.600 INCH, 0.200 INCH HEIGHT, CERAMIC, DDIP-40 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 256K |
| 代理商： | RDC-19220-422Z |
16
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
signals as illustrated in FIGURE 16A. Also, the LSB byte is
always enabled.
FIGURE 16B illustrates a more detailed circuit with delays and
filtering to eliminate potential glitch due to data skew and rise/fall
differences caused by logic loading.
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
LSB +1
LSB
EL
-5 V
CB (ZI)
(ZI)
A
B
FIGURE 16A. INCREMENTAL ENCODER EMULATION
ENCODER EMULATION
The RDC-19220 can be made to emulate incremental optical
encoder output signals, where such an interface is desired. This
is accomplished by tying EL to -5 V, whereby CB becomes Zero
Index (Zl) Logic 1 at all 0s, the LSB+1 becomes A, and the exclu-
sive-or of the LSB and LSB+1 becomes B emulating A QUAD B
LSB +1
LSB
EL
-5 V
RDC-19220
CB/NRP
R1
2k
D1
1N4148
C1
220 pF
4
5
C2
220 pF
13
12
C3
120 pF
9
10
R2
2k
U2A
74AC86
2
1
A
B
NRP
8
6
11
3
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATABLE LOGIC WILL SKEW THE DELAYS.
U2D
74AC86
U2B
74AC86
U2C
74AC86
R3
2k
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