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參數(shù)資料
| 型號(hào)： | RD74VT1G245CLE |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 74V SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PBGA6 |
| 封裝： | 0.90 X 1.40 MM, 0.50 MM HEIGHT, FBGA-6 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 3510K |
| 代理商： | RD74VT1G245CLE |
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RD74VT1G245
Rev.2.00 Apr. 01, 2005 page 12 of 13
Application Information (Cont.)
Figure 2 shows the RD74VT1G245 used in a bidirectional logic level–shifting application. Since the RD74VT1G245
does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between
SYSTEM–1 and SYSTEM–2 when changing directions.
6
1
5
4
2
3
SYSTEM–1
SYSTEM–2
Pullup/Down
or Bus–Hold*
DIR CTRL
I/O–1
I/O–2
VCC1
VCC2
Pullup/Down
or Bus–Hold*
VCC2
Notes:
Following is a sequence that illustrates data transmission from SYSTEM–1 to SYSTEM–2 and then from SYSTEM–2
to SYSTEM–1.
3
4
2
1
L
HI–Z
SYSTEM–2 is getting ready to send data to SYSTEM–1. I/O–1 and
I/O–2 are disabled. The bus–line state depends on Pull–up or Down.*
DIR bit is flipped. I/O–1 and I/O–2 are atill disabled. The bus–line
state depends on Pull–up or Down.*
H
IN
H
SYSTEM–1 data to SYSTEM–2
SYSTEM–2 data to SYSTEM–1
HI–Z
OUT
HI–Z
OUT
HI–Z
IN
L
I/O–2
DESCRIPTION
I/O–1
DIR CTRL
STATE
*: SYSTEM–1 and SYSTEM–2 must use same conditions, i.e., both pull–up or both pull–down.
Figure 2. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the RD74VT1G245 using the following formulas:
1. tZH (DIR to A) = tLZ (DIR to B) + tPLH (B to A)
2. tZL (DIR to A) = tHZ (DIR to B) + tPHL (B to A)
3. tZH (DIR to B) = tLZ (DIR to A) + tPLH (A to B)
4. tZL (DIR to B) = tHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until
an output is expected. For example, if the RD74VT1G245 initially is transmitting from A to B, then the DIR bit is
switched, the B port of the device must be disabled before presenting it with an input. After the B port has been
disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.
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