參數(shù)資料
型號(hào)： RD-19230FG-203
廠商： DATA DEVICE CORP
元件分類： 位置變換器
英文描述： SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64
封裝： 0.520 X 0.520 INCH, GREEN, PLASTIC, QFP-64
文件頁(yè)數(shù)： 6/23頁(yè)
文件大?。?/td> 476K
代理商： RD-19230FG-203
14
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
When this system type does not use the switch resolution on the
fly implementation, large errors and increased settling times
result. The errors exceed 100 LSBs causing the BIT to flag for a
fault condition.
SWITCH ON THE FLY IMPLEMENTATION
The following steps detail switching resolution on the fly. For
additional information refer to the Application Note #AN/MFT-3
“SWITCHING RESOLUTIONS ON THE FLY” available on the
DDC web site at www.ddc-web.com.
1) The SHIFT pin should be controlled synchronously with the
change in resolution. When shift is logic high, the VEL1 com-
ponents will be selected. When shift is logic 0, the VEL2 com-
ponents will be selected.
2) The second set of BW components (CBW2, RB2, CBW2/10)
should typically be of the same value as the first set (CBW1,
RB1, CBW1/10,) and should be installed on VEL2 and VEL SJ2.
Note: Each set of bandwidth components must be chosen to
insure that the tracking rate to BW ratio (listed in
TABLE 2) is not exceeded for the resolution in which
it will be used.
3) The UP/DN line programs the gain of the precharged compo-
nents/amplifier. If the resolution is increasing (UP/DN logic 0),
the gain of the precharge amplifier is set to four. If the resolu-
tion is decreasing (UP/DN logic 1), the gain of the precharge
amplifier is set to 1/4. The gain of the precharge amplifier
should be programmed prior to switching the resolution of the
converter, allowing enough time for the components to settle
to the precharged level. This time will depend on the time con-
stant of the bandwidth components being charged. If switch-
ing is limited to two adjacent resolutions (i.e., 14 and 16) then
the precharge amplifier can be set up to continuously maintain
the appropriate velocity voltage on the deselected compo-
nents, resulting in the fastest possible switching times. See
27
58
+5V
UP/DN
SHIFT
RD-19230
D1
D0
CONTROL
FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY
BETWEEN 14 AND 16 BIT RESOLUTION
UP/DN
The UP/DN input selects the gain of the amplifier driving the de-
selected set of bandwidth components. UP/DN has three input
states. See TABLE 6 to relate input to gain.
BENEFIT OF SWITCHING RESOLUTION
ON THE FLY
Switching resolution on the fly can be used in applications that
require high resolution for accurate position control, and tracking
rates or settling times that are faster than the high resolution
mode will allow.
The RD-19230 can track four times faster for each step down in
resolution (i.e., a step from 16 bits to 14 bits). The velocity output
will be scaled down by a factor of four with each step down in
resolution. For example, if the velocity output is scaled such that
4 Volts = 10 RPS in 16 bit resolution, then the same converter
will output 1 Volt for 10 RPS in 14 bit resolution. To avoid glitch-
es in the velocity output, the second set of bandwidth compo-
nents can be precharged to the expected voltage, and switched
in using the SHIFT input at the same time the resolution is
changed. This will allow for a smooth velocity transition, resulting
in reduced errors and minimal settling time after the change.
FIGURE 17 shows the way the converter behaves during a
change in resolution while tracking at a constant velocity. The
first illustration shows the benefits of switching in precharged
components while changing resolution. The second illustration
shows the result without the benefits of switching on the fly.
The signals that have been recorded are:
1) VEL: velocity output pin on the RD-19230
2) ERROR: this is the analog representation of the error between
the input and the output of the RD-19230
3) D0: an input resolution control line to the RD-19230
4) BIT: built-in-test output pin of the RD-19230
When this system uses the switch resolution on the fly imple-
mentation, the velocity signal immediately assumes the
precharged level of the second set of components, resulting in
small errors and reduced settling times. Notice that the BIT out-
put in FIGURE 17, does not indicate a fault condition.
TABLE 6. PRECHARGE AMPLIFIER
GAIN PROGRAMMING
UP/DN
Logic 0
4
Logic 1
1/4
-5 V
1
GAIN
preset resolution to increase
preset resolution to decrease
dual bandwidth
FUNCTION
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