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R8A66150SP
REJ03F0257-0100
Rev.1.00
Jan.08.2008
Page 2 of 7
BLOCK DIAGRAM
FUNCTION
The R8A66150 is produced by using the silicon gate CMOS technology and has low power dissipation and
high noise margin.
Built in two shift registers for serial in-parallel out (Shift register 2) and parallel in-serial out (Shift register 1)
are constructed independently, R8A66150 is able to read serial input data into a shift register while output
the serial data converting from the parallel data input.
Serial output operation of 12-bit parallel latched data and serial input operation from MCU are started when
/CS is changed from "H" to "L".
12-bits parallel data are latched by the negative edge of /CS and are output from the DO terminal
synchronously to the negative edge of CLK, and also the DI terminal read serial input data from MCU and
are written into the internal shift register 2.
The 13th and following shift clock pulse are ignored and serial input data is masked, and DO terminal
becomes high-impedance ("High-Z").
When /CS is changed from "L" to "H", 12-bits serial data which is read from the DI terminal are output to the
D1~D12 terminals as parallel data.
As the output circuit type of D1~D12 terminals is N-ch open drain output, write data "H" for pins which should
be set to input mode.
C
ont
rol
c
ir
c
u
it
CLK
S
CS
D12 D11 D10
Shift register 1
DO
D12 D11 D10
Parallel output latch
Q12 Q11 Q10
DI
Shift register 2
DI
D12
D11
D10
D3
D2
D1
DO
Vcc
GND GND
D3 D2 D1
Q3 Q2 Q1
D3 D2 D1
Q12 Q11 Q10
Q3 Q2 Q1
Vcc
DO
D1~D12
Vcc
CLK, S, CS, DI
Vcc
Output type
3
6
4
2
710
11
9
8
18
19
20
1
5
S