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SAM9G15 [DATASHEET]
11052E–ATARM–06-Feb-13
Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
1.
2.
Read the Channel Handler Status register to choose an available (disabled) channel.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status regis-
ter. Program the following channel registers:
1.
Write the starting source address in the DMAC_SADDRx register for channel x.
2.
Write the starting destination address in the DMAC_DADDRx register for channel x.
3.
Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in
Table 31-3
on page 456
. Program the DMAC_DSCRx register with ‘0’.
4.
Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for
channel x. For example, in the register, you can program the following:
i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
ii. Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_WIDTH field.
Transfer width for the destination in the DST_WIDTH field.
Source AHB master interface layer in the SIF field where source resides.
Destination AHB master interface layer in the DIF field where destination resides.
Incrementing/decrementing or fixed address for source in SRC_INCR field.
Incrementing/decrementing or fixed address for destination in DST_INCR field.
5.
If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx
register for channel x.
6.
If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for
channel x.
7.
Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the
reload bits, DMAC_CFGx.SRC_REP, DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled.
i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_h2SEL
bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign
handshaking interface to the source and destination peripheral. This requires programming the SRC_PER
and DST_PER bits, respectively.
After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_CHER.ENAx bit where the channel number is. Make sure that bit 0 of the DMAC_EN register is enabled.
Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-
memory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carries out
the buffer transfer.
When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx, DMAC_DADDRx and
DMAC_CTRLAx registers. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples
the row number as shown in
Table 31-3 on page 456
. If the DMAC is in Row 1, then the DMAC transfer has com-
pleted. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can
either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll
for the Channel Enable in the Channel Status Register (DMAC_CHSR.ENAx) until it is disabled, to detect when
the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
The DMAC transfer proceeds as follows:
1.
If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel
number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has com-
pleted. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to
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3.
4.
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6.