參數(shù)資料
型號: R5F6456HLFD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 4/37頁
文件大小: 881K
代理商: R5F6456HLFD
R8C/16 Group, R8C/17 Group
2. Central Processing Unit (CPU)
Rev.2.00
Jan 30, 2006
Page 10 of 35
REJ03B0101-0200
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and
FB comprise a register bank. Two sets of register banks are provided.
Figure 2.1
CPU Register
R2
b31
b15
b8b7
b0
Data Register (1)
Address Register (1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15
b19
b0
INTBL
FB
Frame Bass Register (1)
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
Interrupt Table Register
b19
b0
USP
Program Counter
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
PC
FLG
Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Bit
Processor Interrupt Priority Level
Reserved Bit
C
IPL
D
Z
S
B
O
I
U
b15
b0
b15
b0
b15
b0
b8
b7
NOTES:
1. A register bank comprises these registers. Two sets of register banks are provided.
R0L (low-order of R0)
R1H (high-order of R1)
R1L (low-order of R1)
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