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參數(shù)資料
| 型號： | R5F6421GJFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 35/50頁 |
| 文件大?。?/td> | 777K |
| 代理商： | R5F6421GJFB |
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113
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values. If OCR1A is used to define the TOP value (WGM1[3:0] = 11) and COM1A1:0 = 1,
the OC1A output will toggle with a 50% duty cycle.
16.9.5
Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0
= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase
and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Com-
pare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x
while upcounting, and set on the compare match while down counting. In inverting Compare Output mode, the
operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the sin-
gle-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 16-8 and Figure 16-9).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit
(ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and
changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct and frequency correct PWM mode is shown on Figure 16-9. The figure shows phase and fre-
quency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between
OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs.
Figure 16-9. Phase and Frequency Correct PWM Mode, timing diagram.
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated
with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the
R
PFCPWM
TOP
1
+
log
2
log
-----------------------------------
=
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
2
3
4
TCNTn
Period
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6421GKFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6421GLFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6421HJFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6421HKFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6421HLFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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