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參數(shù)資料
| 型號(hào)： | R5F64211KFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 9/50頁 |
| 文件大小： | 777K |
| 代理商： | R5F64211KFB |
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REJ03B0237-0050 Rev.0.50 Jul 31, 2008
Page 15 of 111
Under development
Preliminary Specification
This is a preliminary specification and is subject to change.
R32C/121 Group
2. Central Processing Unit (CPU)
2.1
General Purpose Registers
2.1.1
Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into the upper and the lower 16-bit registers, e.g. R2R0 can be
divided into R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: the upper (R2h,
and R3H), the mid-upper (R2L, and R3L), the mid-lower (R0H, and R1H), and the lower (R0L, and
R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have the similar functions to the data registers. They are also used for address
register indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP). They are switched by the U flag. Refer to 2.1.8 “Flag Register (FLG)” for details on the U
flag.
The stack pointer (USP/ISP) to be used can be switched by the stack pointer select flag (U flag). This
flag is bit 7 in the flag register (FLG).
A multiple of 4 should be set to USP or ISP, which enables faster interrupt sequence due to less
memory access.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag has the carry, borrow, shifted-out bit, etc. generated in the arithmetic logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is used exclusively for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when an operation results in 0; in all other cases, this flag becomes 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when an operation results in a negative; in all other cases, this flag becomes 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F64211LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212JFB | 制造商:Renesas Electronics Corporation 功能描述: |
| R5F64212KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64213JFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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